From patchwork Wed Dec 14 12:59:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13073055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07B00C4167B for ; Wed, 14 Dec 2022 13:02:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238503AbiLNNCC (ORCPT ); Wed, 14 Dec 2022 08:02:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238320AbiLNNBL (ORCPT ); Wed, 14 Dec 2022 08:01:11 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69582165B0 for ; Wed, 14 Dec 2022 05:00:52 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id s7so3249557plk.5 for ; Wed, 14 Dec 2022 05:00:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GVhftXkOyDrHisXtuBAfFezrQnFr2dvDm7Sl7pD6BIE=; b=kIDUfCKrGdJ5H0JCcr9M2LTV7mdeO+VVcDhpZuaZUyq9+QRh7tKi4Q+QMm6Ps28++r NTNaynC8/VrqkeuPrJWm41gnqeMeNUKLmshYv/ArGEVVWEJNdI4BtmJHzZSRKSUn29Rd CP53wpvatkyAL4QHeOK+g5EqsFC2iSihoNV9o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GVhftXkOyDrHisXtuBAfFezrQnFr2dvDm7Sl7pD6BIE=; b=1F4LRnnUzf+mtyH+Xa1N27Hv2HfC7KzGplNzYlrgYrmTDWzKd9Fd3tyA15F5f40W7H KaF4f2VVeaM9Ub1d0ctjXbENkuejwJP8DMBvpxAybHC+YW6TCJUQx4THXVRk42JvHzhr k5FZjFIJk9HdSJZvFvOjYxPIX6sDtOR+nT7Cxjb7sU7O2F4PcsNcurTqNQflRqQi+AFA R0gwVerw5V85DR3GNpybvEiKaYvMrczvHH5RpT0J/7MVaMX1g4Tsk7V+YW8/GNgMzVvK q6qhClJtYvspRucp+hIdxZr/E8dRWJh2r45M3TVfpaPj4xof5ESNtm4NGgjcXuu+iQwM GSLQ== X-Gm-Message-State: ANoB5pnjttFKaj39mFOkJkofffbVizNtvo73VfjO+GLT3s5Xjg5Sn8GJ PKevueTwo9BeWPbjKa6egd5sfw== X-Google-Smtp-Source: AA0mqf7kI2zgP7bgEMAGvS5Q4cLMWOfxZyJyVf6dG7VkuwOehH/io5n/bsvuivhMXM1JbFKTq3pibQ== X-Received: by 2002:a17:902:788e:b0:189:efe7:df8d with SMTP id q14-20020a170902788e00b00189efe7df8dmr24006481pll.43.1671022851498; Wed, 14 Dec 2022 05:00:51 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:5e03:faf:846e:352d]) by smtp.gmail.com with ESMTPSA id ix17-20020a170902f81100b001895f7c8a71sm1838651plb.97.2022.12.14.05.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 05:00:51 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Fancy Fang , Tim Harvey , Michael Nazzareno Trimarchi , Adam Ford , Neil Armstrong , Robert Foss , Laurent Pinchart , Tommaso Merciai , Marek Vasut Cc: Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula , Jagan Teki Subject: [PATCH v10 11/18] drm: exynos: dsi: Add atomic_get_input_bus_fmts Date: Wed, 14 Dec 2022 18:29:00 +0530 Message-Id: <20221214125907.376148-12-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221214125907.376148-1-jagan@amarulasolutions.com> References: <20221214125907.376148-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Finding the right input bus format throughout the pipeline is hard so add atomic_get_input_bus_fmts callback and initialize with the proper input format from list of supported output formats. This format can be used in pipeline for negotiating bus format between the DSI-end of this bridge and the other component closer to pipeline components. List of Pixel formats are taken from, AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 3.7.4 Pixel formats Table 14. DSI pixel packing formats Tested-by: Marek Szyprowski Signed-off-by: Jagan Teki Reviewed-by: Frieder Schrempf --- Changes for v10: - none Changes for v9: - added MEDIA_BUS_FMT_FIXED - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt list is unsupported. - added MEDIA_BUS_FMT_YUYV10_1X20, MEDIA_BUS_FMT_YUYV12_1X24 Changes for v8: - added pixel formats supported by NXP AN13573 i.MX 8/RT MIPI DSI/CSI-2 Changes for v7 - v4: - none Changes for v3: - include media-bus-format.h Changes for v2: - none Changes for v1: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 69 +++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 36820a7b5884..bb3d6a7fa84e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1467,6 +1468,73 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +/* + * This pixel output formats list referenced from, + * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 + * 3.7.4 Pixel formats + * Table 14. DSI pixel packing formats + */ +static const u32 exynos_dsi_pixel_output_fmts[] = { + MEDIA_BUS_FMT_YUYV10_1X20, + MEDIA_BUS_FMT_YUYV12_1X24, + MEDIA_BUS_FMT_UYVY8_1X16, + MEDIA_BUS_FMT_RGB101010_1X30, + MEDIA_BUS_FMT_RGB121212_1X36, + MEDIA_BUS_FMT_RGB565_1X16, + MEDIA_BUS_FMT_RGB666_1X18, + MEDIA_BUS_FMT_RGB888_1X24, + + MEDIA_BUS_FMT_FIXED, +}; + +static bool exynos_dsi_pixel_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(exynos_dsi_pixel_output_fmts); i++) { + if (exynos_dsi_pixel_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +exynos_dsi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + if (!exynos_dsi_pixel_output_fmt_supported(output_fmt)) + /* + * Some bridge/display drivers are still not able to pass the + * correct format, so handle those pipelines by falling back + * to the default format till the supported formats finalized. + */ + output_fmt = MEDIA_BUS_FMT_RGB888_1X24; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_FIXED: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + break; + default: + input_fmts[0] = output_fmt; + break; + } + + *num_input_fmts = 1; + + return input_fmts; +} + static int exynos_dsi_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, @@ -1515,6 +1583,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_get_input_bus_fmts = exynos_dsi_atomic_get_input_bus_fmts, .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable,