diff mbox series

[08/16] PCI: samsung: Rename exynos_pcie to samsung_pcie

Message ID 20230214121333.1837-9-shradha.t@samsung.com (mailing list archive)
State New
Headers show
Series [01/16] dt-bindings: PCI: Rename Exynos PCIe binding to Samsung PCIe | expand

Commit Message

Shradha Todi Feb. 14, 2023, 12:13 p.m. UTC 
The platform specific structure being used is named
exynos_pcie. Changing it to samsung_pcie for making it
generic.

Suggested-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
---
 drivers/pci/controller/dwc/pci-samsung.c | 190 +++++++++++------------
 1 file changed, 95 insertions(+), 95 deletions(-)

Comments

Krzysztof Kozlowski Feb. 16, 2023, 11:07 a.m. UTC | #1 
On 14/02/2023 13:13, Shradha Todi wrote:
> The platform specific structure being used is named
> exynos_pcie. Changing it to samsung_pcie for making it
> generic.
> 
> Suggested-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
>  drivers/pci/controller/dwc/pci-samsung.c | 190 +++++++++++------------
>  1 file changed, 95 insertions(+), 95 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c
> index d5adf1017a05..be0177fcd763 100644
> --- a/drivers/pci/controller/dwc/pci-samsung.c
> +++ b/drivers/pci/controller/dwc/pci-samsung.c
> @@ -23,7 +23,7 @@
>  
>  #include "pcie-designware.h"
>  
> -#define to_exynos_pcie(x)	dev_get_drvdata((x)->dev)
> +#define to_samsung_pcie(x)	dev_get_drvdata((x)->dev)
>  
>  /* PCIe APPL registers */
>  #define EXYNOS_PCIE_IRQ_PULSE			0x000
> @@ -51,7 +51,7 @@
>  #define EXYNOS_PCIE_APPL_SLV_ARMISC		0x120
>  #define EXYNOS_PCIE_APPL_SLV_DBI_ENABLE	BIT(21)
>  
> -struct exynos_pcie {
> +struct samsung_pcie {

No, I don't see benefit of this at all. How we call stuff inside driver
is not related whether this is for Tesla or Exynos. We could even call
it "pony". :) Thus renamings just to support new variant of Samsung
device is not a good reason.

Unless all of the old "exynos" names will be soon needed for some
exynos-specific variants?

Best regards,
Krzysztof
Pankaj Dubey March 2, 2023, 12:32 p.m. UTC | #2 
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Thursday, February 16, 2023 4:37 PM
> To: Shradha Todi <shradha.t@samsung.com>; lpieralisi@kernel.org;
> kw@linux.com; robh@kernel.org; bhelgaas@google.com;
> krzysztof.kozlowski+dt@linaro.org; alim.akhtar@samsung.com;
> jingoohan1@gmail.com; Sergey.Semin@baikalelectronics.ru;
> lukas.bulwahn@gmail.com; hongxing.zhu@nxp.com; tglx@linutronix.de;
> m.szyprowski@samsung.com; jh80.chung@samsung.co;
> pankaj.dubey@samsung.com
> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 08/16] PCI: samsung: Rename exynos_pcie to
> samsung_pcie
> 
> On 14/02/2023 13:13, Shradha Todi wrote:
> > The platform specific structure being used is named exynos_pcie.
> > Changing it to samsung_pcie for making it generic.
> >
> > Suggested-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> > Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> > ---
> >  drivers/pci/controller/dwc/pci-samsung.c | 190
> > +++++++++++------------
> >  1 file changed, 95 insertions(+), 95 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-samsung.c
> > b/drivers/pci/controller/dwc/pci-samsung.c
> > index d5adf1017a05..be0177fcd763 100644
> > --- a/drivers/pci/controller/dwc/pci-samsung.c
> > +++ b/drivers/pci/controller/dwc/pci-samsung.c
> > @@ -23,7 +23,7 @@
> >
> >  #include "pcie-designware.h"
> >
> > -#define to_exynos_pcie(x)	dev_get_drvdata((x)->dev)
> > +#define to_samsung_pcie(x)	dev_get_drvdata((x)->dev)
> >
> >  /* PCIe APPL registers */
> >  #define EXYNOS_PCIE_IRQ_PULSE			0x000
> > @@ -51,7 +51,7 @@
> >  #define EXYNOS_PCIE_APPL_SLV_ARMISC		0x120
> >  #define EXYNOS_PCIE_APPL_SLV_DBI_ENABLE	BIT(21)
> >
> > -struct exynos_pcie {
> > +struct samsung_pcie {
> 
> No, I don't see benefit of this at all. How we call stuff inside driver is not related
> whether this is for Tesla or Exynos. We could even call it "pony". :) Thus
> renamings just to support new variant of Samsung device is not a good reason.
> 
Whole intention of this whole series was to make exynos-pcie driver to support for all Samsung manufactured SoCs be it Exynos series or custom ASIC such as fsd, artpect-v8. 

While doing so, we feel for better readability and conveying better names for files, structs, internal APIs will help developers for understanding and reusing it. For example we know that clock initialization will remain common (thanks for bulk_clk_xxx APIs) so we kept APIs for handling clocks starting with samsung_clk_xxxx, but if we have to implement two variant of APIs, or struct targeting different platforms it would be good if they have platform specific prefixes. This will help in grep or future code maintenance. 

Though technically all these can be done even without renaming, but if we see no impact as such, so why not use better names?
> Unless all of the old "exynos" names will be soon needed for some exynos-
> specific variants?
> 

No we don't have any such plans.

> Best regards,
> Krzysztof
Krzysztof Kozlowski March 3, 2023, 10:06 a.m. UTC | #3 
On 02/03/2023 13:32, Pankaj Dubey wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Thursday, February 16, 2023 4:37 PM
>> To: Shradha Todi <shradha.t@samsung.com>; lpieralisi@kernel.org;
>> kw@linux.com; robh@kernel.org; bhelgaas@google.com;
>> krzysztof.kozlowski+dt@linaro.org; alim.akhtar@samsung.com;
>> jingoohan1@gmail.com; Sergey.Semin@baikalelectronics.ru;
>> lukas.bulwahn@gmail.com; hongxing.zhu@nxp.com; tglx@linutronix.de;
>> m.szyprowski@samsung.com; jh80.chung@samsung.co;
>> pankaj.dubey@samsung.com
>> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
>> kernel@vger.kernel.org
>> Subject: Re: [PATCH 08/16] PCI: samsung: Rename exynos_pcie to
>> samsung_pcie
>>
>> On 14/02/2023 13:13, Shradha Todi wrote:
>>> The platform specific structure being used is named exynos_pcie.
>>> Changing it to samsung_pcie for making it generic.
>>>
>>> Suggested-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>>> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
>>> ---
>>>  drivers/pci/controller/dwc/pci-samsung.c | 190
>>> +++++++++++------------
>>>  1 file changed, 95 insertions(+), 95 deletions(-)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pci-samsung.c
>>> b/drivers/pci/controller/dwc/pci-samsung.c
>>> index d5adf1017a05..be0177fcd763 100644
>>> --- a/drivers/pci/controller/dwc/pci-samsung.c
>>> +++ b/drivers/pci/controller/dwc/pci-samsung.c
>>> @@ -23,7 +23,7 @@
>>>
>>>  #include "pcie-designware.h"
>>>
>>> -#define to_exynos_pcie(x)	dev_get_drvdata((x)->dev)
>>> +#define to_samsung_pcie(x)	dev_get_drvdata((x)->dev)
>>>
>>>  /* PCIe APPL registers */
>>>  #define EXYNOS_PCIE_IRQ_PULSE			0x000
>>> @@ -51,7 +51,7 @@
>>>  #define EXYNOS_PCIE_APPL_SLV_ARMISC		0x120
>>>  #define EXYNOS_PCIE_APPL_SLV_DBI_ENABLE	BIT(21)
>>>
>>> -struct exynos_pcie {
>>> +struct samsung_pcie {
>>
>> No, I don't see benefit of this at all. How we call stuff inside driver is not related
>> whether this is for Tesla or Exynos. We could even call it "pony". :) Thus
>> renamings just to support new variant of Samsung device is not a good reason.
>>
> Whole intention of this whole series was to make exynos-pcie driver to support for all Samsung manufactured SoCs be it Exynos series or custom ASIC such as fsd, artpect-v8. 

But the patches does not do it, at least mostly. It only renames which
does not bring any support... what's more, such renames without actual
context - support for the new devices - is a bit pointless.

> 
> While doing so, we feel for better readability and conveying better names for files, structs, internal APIs will help developers for understanding and reusing it. For example we know that clock initialization will remain common (thanks for bulk_clk_xxx APIs) so we kept APIs for handling clocks starting with samsung_clk_xxxx, but if we have to implement two variant of APIs, or struct targeting different platforms it would be good if they have platform specific prefixes. This will help in grep or future code maintenance.

Without context it's impossible to judge whether this makes any sense.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c
index d5adf1017a05..be0177fcd763 100644
--- a/drivers/pci/controller/dwc/pci-samsung.c
+++ b/drivers/pci/controller/dwc/pci-samsung.c
@@ -23,7 +23,7 @@ 
 
 #include "pcie-designware.h"
 
-#define to_exynos_pcie(x)	dev_get_drvdata((x)->dev)
+#define to_samsung_pcie(x)	dev_get_drvdata((x)->dev)
 
 /* PCIe APPL registers */
 #define EXYNOS_PCIE_IRQ_PULSE			0x000
@@ -51,7 +51,7 @@ 
 #define EXYNOS_PCIE_APPL_SLV_ARMISC		0x120
 #define EXYNOS_PCIE_APPL_SLV_DBI_ENABLE	BIT(21)
 
-struct exynos_pcie {
+struct samsung_pcie {
 	struct dw_pcie			pci;
 	void __iomem			*appl_base;
 	struct clk_bulk_data		*clks;
@@ -60,23 +60,23 @@  struct exynos_pcie {
 	struct regulator_bulk_data	supplies[2];
 };
 
-static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep)
+static int exynos_pcie_init_clk_resources(struct samsung_pcie *sp)
 {
-	struct device *dev = ep->pci.dev;
+	struct device *dev = sp->pci.dev;
 	int ret;
 
-	ret = devm_clk_bulk_get_all(dev, &ep->clks);
+	ret = devm_clk_bulk_get_all(dev, &sp->clks);
 	if (ret < 0)
 		return ret;
 
-	ep->clk_cnt = ret;
+	sp->clk_cnt = ret;
 
-	return clk_bulk_prepare_enable(ep->clk_cnt, ep->clks);
+	return clk_bulk_prepare_enable(sp->clk_cnt, sp->clks);
 }
 
-static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep)
+static void exynos_pcie_deinit_clk_resources(struct samsung_pcie *sp)
 {
-	clk_bulk_disable_unprepare(ep->clk_cnt, ep->clks);
+	clk_bulk_disable_unprepare(sp->clk_cnt, sp->clks);
 }
 
 static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
@@ -89,115 +89,115 @@  static u32 exynos_pcie_readl(void __iomem *base, u32 reg)
 	return readl(base + reg);
 }
 
-static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
+static void exynos_pcie_sideband_dbi_w_mode(struct samsung_pcie *sp, bool on)
 {
 	u32 val;
 
-	val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_SLV_AWMISC);
+	val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_AWMISC);
 	if (on)
 		val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE;
 	else
 		val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE;
-	exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_APPL_SLV_AWMISC);
+	exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_AWMISC);
 }
 
-static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
+static void exynos_pcie_sideband_dbi_r_mode(struct samsung_pcie *sp, bool on)
 {
 	u32 val;
 
-	val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_SLV_ARMISC);
+	val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_ARMISC);
 	if (on)
 		val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE;
 	else
 		val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE;
-	exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_APPL_SLV_ARMISC);
+	exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_ARMISC);
 }
 
-static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
+static void exynos_pcie_assert_core_reset(struct samsung_pcie *sp)
 {
 	u32 val;
 
-	val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_CORE_RESET);
+	val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET);
 	val &= ~EXYNOS_PCIE_CORE_RESET_ENABLE;
-	exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_CORE_RESET);
-	exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_STICKY_RESET);
-	exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_NONSTICKY_RESET);
+	exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET);
+	exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_STICKY_RESET);
+	exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_NONSTICKY_RESET);
 }
 
-static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
+static void exynos_pcie_deassert_core_reset(struct samsung_pcie *sp)
 {
 	u32 val;
 
-	val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_CORE_RESET);
+	val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET);
 	val |= EXYNOS_PCIE_CORE_RESET_ENABLE;
 
-	exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_CORE_RESET);
-	exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_STICKY_RESET);
-	exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_NONSTICKY_RESET);
-	exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_APP_INIT_RESET);
-	exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_APP_INIT_RESET);
+	exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET);
+	exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_STICKY_RESET);
+	exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_NONSTICKY_RESET);
+	exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_APP_INIT_RESET);
+	exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_APP_INIT_RESET);
 }
 
 static int exynos_pcie_start_link(struct dw_pcie *pci)
 {
-	struct exynos_pcie *ep = to_exynos_pcie(pci);
+	struct samsung_pcie *sp = to_samsung_pcie(pci);
 	u32 val;
 
-	val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_SW_WAKE);
+	val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_SW_WAKE);
 	val &= ~EXYNOS_PCIE_BUS_EN;
-	exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_SW_WAKE);
+	exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_SW_WAKE);
 
 	/* assert LTSSM enable */
-	exynos_pcie_writel(ep->appl_base, EXYNOS_PCIE_APPL_LTSSM_ENABLE,
+	exynos_pcie_writel(sp->appl_base, EXYNOS_PCIE_APPL_LTSSM_ENABLE,
 			  EXYNOS_PCIE_APP_LTSSM_ENABLE);
 	return 0;
 }
 
-static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
+static void exynos_pcie_clear_irq_pulse(struct samsung_pcie *sp)
 {
-	u32 val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_IRQ_PULSE);
+	u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_IRQ_PULSE);
 
-	exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_IRQ_PULSE);
+	exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_PULSE);
 }
 
 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
 {
-	struct exynos_pcie *ep = arg;
+	struct samsung_pcie *sp = arg;
 
-	exynos_pcie_clear_irq_pulse(ep);
+	exynos_pcie_clear_irq_pulse(sp);
 	return IRQ_HANDLED;
 }
 
-static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
+static void exynos_pcie_enable_irq_pulse(struct samsung_pcie *sp)
 {
 	u32 val = EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT |
 		  EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT;
 
-	exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_IRQ_EN_PULSE);
-	exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL);
-	exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL);
+	exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_EN_PULSE);
+	exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL);
+	exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL);
 }
 
 static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
 				u32 reg, size_t size)
 {
-	struct exynos_pcie *ep = to_exynos_pcie(pci);
+	struct samsung_pcie *sp = to_samsung_pcie(pci);
 	u32 val;
 
-	exynos_pcie_sideband_dbi_r_mode(ep, true);
+	exynos_pcie_sideband_dbi_r_mode(sp, true);
 	dw_pcie_read(base + reg, size, &val);
-	exynos_pcie_sideband_dbi_r_mode(ep, false);
+	exynos_pcie_sideband_dbi_r_mode(sp, false);
 	return val;
 }
 
 static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
 				  u32 reg, size_t size, u32 val)
 {
-	struct exynos_pcie *ep = to_exynos_pcie(pci);
+	struct samsung_pcie *sp = to_samsung_pcie(pci);
 
-	exynos_pcie_sideband_dbi_w_mode(ep, true);
+	exynos_pcie_sideband_dbi_w_mode(sp, true);
 	dw_pcie_write(base + reg, size, val);
-	exynos_pcie_sideband_dbi_w_mode(ep, false);
+	exynos_pcie_sideband_dbi_w_mode(sp, false);
 }
 
 static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
@@ -231,8 +231,8 @@  static struct pci_ops exynos_pci_ops = {
 
 static int exynos_pcie_link_up(struct dw_pcie *pci)
 {
-	struct exynos_pcie *ep = to_exynos_pcie(pci);
-	u32 val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_RDLH_LINKUP);
+	struct samsung_pcie *sp = to_samsung_pcie(pci);
+	u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_RDLH_LINKUP);
 
 	return (val & EXYNOS_PCIE_APPL_XMLH_LINKUP);
 }
@@ -240,17 +240,17 @@  static int exynos_pcie_link_up(struct dw_pcie *pci)
 static int exynos_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-	struct exynos_pcie *ep = to_exynos_pcie(pci);
+	struct samsung_pcie *sp = to_samsung_pcie(pci);
 
 	pp->bridge->ops = &exynos_pci_ops;
 
-	exynos_pcie_assert_core_reset(ep);
+	exynos_pcie_assert_core_reset(sp);
 
-	phy_init(ep->phy);
-	phy_power_on(ep->phy);
+	phy_init(sp->phy);
+	phy_power_on(sp->phy);
 
-	exynos_pcie_deassert_core_reset(ep);
-	exynos_pcie_enable_irq_pulse(ep);
+	exynos_pcie_deassert_core_reset(sp);
+	exynos_pcie_enable_irq_pulse(sp);
 
 	return 0;
 }
@@ -259,10 +259,10 @@  static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
 	.host_init = exynos_pcie_host_init,
 };
 
-static int exynos_add_pcie_port(struct exynos_pcie *ep,
+static int exynos_add_pcie_port(struct samsung_pcie *sp,
 				       struct platform_device *pdev)
 {
-	struct dw_pcie *pci = &ep->pci;
+	struct dw_pcie *pci = &sp->pci;
 	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = &pdev->dev;
 	int ret;
@@ -272,7 +272,7 @@  static int exynos_add_pcie_port(struct exynos_pcie *ep,
 		return pp->irq;
 
 	ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
-			       IRQF_SHARED, "exynos-pcie", ep);
+			       IRQF_SHARED, "exynos-pcie", sp);
 	if (ret) {
 		dev_err(dev, "failed to request irq\n");
 		return ret;
@@ -300,95 +300,95 @@  static const struct dw_pcie_ops dw_pcie_ops = {
 static int exynos_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct exynos_pcie *ep;
+	struct samsung_pcie *sp;
 	struct device_node *np = dev->of_node;
 	int ret;
 
-	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
-	if (!ep)
+	sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
+	if (!sp)
 		return -ENOMEM;
 
-	ep->pci.dev = dev;
-	ep->pci.ops = &dw_pcie_ops;
+	sp->pci.dev = dev;
+	sp->pci.ops = &dw_pcie_ops;
 
-	ep->phy = devm_of_phy_get(dev, np, NULL);
-	if (IS_ERR(ep->phy))
-		return PTR_ERR(ep->phy);
+	sp->phy = devm_of_phy_get(dev, np, NULL);
+	if (IS_ERR(sp->phy))
+		return PTR_ERR(sp->phy);
 
 	/* Application logic registers */
-	ep->appl_base = devm_platform_ioremap_resource_byname(pdev, "appl");
-	if (IS_ERR(ep->appl_base))
-		return PTR_ERR(ep->appl_base);
+	sp->appl_base = devm_platform_ioremap_resource_byname(pdev, "appl");
+	if (IS_ERR(sp->appl_base))
+		return PTR_ERR(sp->appl_base);
 
-	ret = exynos_pcie_init_clk_resources(ep);
+	ret = exynos_pcie_init_clk_resources(sp);
 	if (ret < 0)
 		return ret;
 
-	ep->supplies[0].supply = "vdd18";
-	ep->supplies[1].supply = "vdd10";
-	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies),
-				      ep->supplies);
+	sp->supplies[0].supply = "vdd18";
+	sp->supplies[1].supply = "vdd10";
+	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sp->supplies),
+				      sp->supplies);
 	if (ret)
 		return ret;
 
-	ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
+	ret = regulator_bulk_enable(ARRAY_SIZE(sp->supplies), sp->supplies);
 	if (ret)
 		return ret;
 
-	platform_set_drvdata(pdev, ep);
+	platform_set_drvdata(pdev, sp);
 
-	ret = exynos_add_pcie_port(ep, pdev);
+	ret = exynos_add_pcie_port(sp, pdev);
 	if (ret < 0)
 		goto fail_probe;
 
 	return 0;
 
 fail_probe:
-	phy_exit(ep->phy);
-	regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
-	exynos_pcie_deinit_clk_resources(ep);
+	phy_exit(sp->phy);
+	regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies);
+	exynos_pcie_deinit_clk_resources(sp);
 
 	return ret;
 }
 
 static int __exit exynos_pcie_remove(struct platform_device *pdev)
 {
-	struct exynos_pcie *ep = platform_get_drvdata(pdev);
+	struct samsung_pcie *sp = platform_get_drvdata(pdev);
 
-	dw_pcie_host_deinit(&ep->pci.pp);
-	exynos_pcie_assert_core_reset(ep);
-	phy_power_off(ep->phy);
-	phy_exit(ep->phy);
-	exynos_pcie_deinit_clk_resources(ep);
-	regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
+	dw_pcie_host_deinit(&sp->pci.pp);
+	exynos_pcie_assert_core_reset(sp);
+	phy_power_off(sp->phy);
+	phy_exit(sp->phy);
+	exynos_pcie_deinit_clk_resources(sp);
+	regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies);
 
 	return 0;
 }
 
 static int exynos_pcie_suspend_noirq(struct device *dev)
 {
-	struct exynos_pcie *ep = dev_get_drvdata(dev);
+	struct samsung_pcie *sp = dev_get_drvdata(dev);
 
-	exynos_pcie_assert_core_reset(ep);
-	phy_power_off(ep->phy);
-	phy_exit(ep->phy);
-	regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
+	exynos_pcie_assert_core_reset(sp);
+	phy_power_off(sp->phy);
+	phy_exit(sp->phy);
+	regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies);
 
 	return 0;
 }
 
 static int exynos_pcie_resume_noirq(struct device *dev)
 {
-	struct exynos_pcie *ep = dev_get_drvdata(dev);
-	struct dw_pcie *pci = &ep->pci;
+	struct samsung_pcie *sp = dev_get_drvdata(dev);
+	struct dw_pcie *pci = &sp->pci;
 	struct dw_pcie_rp *pp = &pci->pp;
 	int ret;
 
-	ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
+	ret = regulator_bulk_enable(ARRAY_SIZE(sp->supplies), sp->supplies);
 	if (ret)
 		return ret;
 
-	/* exynos_pcie_host_init controls ep->phy */
+	/* exynos_pcie_host_init controls sp->phy */
 	exynos_pcie_host_init(pp);
 	dw_pcie_setup_rc(pp);
 	exynos_pcie_start_link(pci);