From patchwork Mon Feb 27 11:39:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13153351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD53CC64ED8 for ; Mon, 27 Feb 2023 11:40:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229658AbjB0Lkm (ORCPT ); Mon, 27 Feb 2023 06:40:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229608AbjB0Lkl (ORCPT ); Mon, 27 Feb 2023 06:40:41 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FDB112878 for ; Mon, 27 Feb 2023 03:40:40 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id c1so6386833plg.4 for ; Mon, 27 Feb 2023 03:40:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LU+ldY5CPu/D8luQ9aqgfh0M/OSOuFnng/b9Q9chcZ8=; b=Y96TmNpy5J3JaTUYKh9SD5RiwUnngbBU0EyuHEDu6wfRVQsOczLuojP0qvDFvA1qw9 ky6Ky9sc/FJpw9B0fetNe6zRrFILD6/v5p6NoeszxBWmbSmQq7lq/cC0ldY6ceqyqE1e brcd7Ajx4ZHoXYAw/+RpbX0zeHcobc/BVvGnQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LU+ldY5CPu/D8luQ9aqgfh0M/OSOuFnng/b9Q9chcZ8=; b=vNj2DbYcKWfPTS9lDD3z2WohzCQWv1Wu4OLEJGL4TsAoTCr0KeiFwMvBaATPOwkviW IpMQtvRX7sgj00t9g4NppCyWmZYN6ySIwUlvVxRmhA8dlB8HLhNffFFMDP3DgLoQjGbJ uywuqZDS2FkXSGgil6KsaX+1KC6/NZF3Mkm1h4CJB7Zfkaq5ZH+uAFZIj5SREPcAzmJK hDvgohISFB/kQJO1MzeYyPuqxBzab6yE2vqoeOzXwu51gxH2r7946Coz5CowhK1idNRL 2lu54VpRyR1897dGU8zl7GAf9ql9UMP1ATqf8JUNmfs+dPxkEEJ0WNBJfqBTVkWDrK9I SDkQ== X-Gm-Message-State: AO0yUKWPLtTbC8NfqhAbbvjdhW9wNUua4zZP+zvg95FhpzaHE/tlSW6q w57p78ON9DuADhJ/DggA2uAntA== X-Google-Smtp-Source: AK7set8FtrahxTcHtM0pf6viM1IDqT3/dJUsoNRiG1+tp3Nmrc/rwCiAWH43BsBc4NUV8iUGrfdxcw== X-Received: by 2002:a17:903:228d:b0:199:4a00:9788 with SMTP id b13-20020a170903228d00b001994a009788mr27406857plh.19.1677498039672; Mon, 27 Feb 2023 03:40:39 -0800 (PST) Received: from localhost.localdomain ([94.140.8.120]) by smtp.gmail.com with ESMTPSA id k10-20020a170902ba8a00b0019c919bccf8sm4395277pls.86.2023.02.27.03.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 03:40:39 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Laurent Pinchart , Marek Vasut Cc: Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula , Jagan Teki Subject: [PATCH v13 09/18] drm: exynos: dsi: Add atomic check Date: Mon, 27 Feb 2023 17:09:16 +0530 Message-Id: <20230227113925.875425-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227113925.875425-1-jagan@amarulasolutions.com> References: <20230227113925.875425-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Look like an explicit fixing up of mode_flags is required for DSIM IP present in i.MX8M Mini/Nano SoCs. At least the LCDIF + DSIM needs active low sync polarities in order to correlate the correct sync flags of the surrounding components in the chain to make sure the whole pipeline can work properly. On the other hand the i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 says. "13.6.3.5.2 RGB interface Vsync, Hsync, and VDEN are active high signals." i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 3.6.3.5.2 RGB interface i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 13.6.2.7.2 RGB interface both claim "Vsync, Hsync, and VDEN are active high signals.", the LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. No clear evidence about whether it can be documentation issues or something, so added proper comments on the code. Comments are suggested by Marek Vasut. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Signed-off-by: Jagan Teki --- Changes for v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - fix commit message Changes for v10, v9: - none Changes for v8: - update the comments about sync signals polarities - added clear commit message by including i.MX8M Nano details Changes for v7: - fix the hw_type checking logic Changes for v6: - none Changes for v5: - rebase based new bridge changes [mszyprow] - remove DSIM_QUIRK_FIXUP_SYNC_POL - add hw_type check for sync polarities change. Changes for v4: - none Changes for v3: - add DSIM_QUIRK_FIXUP_SYNC_POL to handle mode_flasg fixup Changes for v2: - none Changes for v1: - fix mode flags in atomic_check instead of mode_fixup drivers/gpu/drm/exynos/exynos_drm_dsi.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 5723d91ff686..22e3bdcf5494 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -264,6 +264,7 @@ enum exynos_dsi_type { DSIM_TYPE_EXYNOS5410, DSIM_TYPE_EXYNOS5422, DSIM_TYPE_EXYNOS5433, + DSIM_TYPE_IMX8MM, DSIM_TYPE_COUNT, }; @@ -1466,6 +1467,32 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +static int exynos_dsi_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct exynos_dsi *dsi = bridge_to_dsi(bridge); + struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + + /* + * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM + * inverts HS/VS/DE sync signals polarity, therefore, while + * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 + * 13.6.3.5.2 RGB interface + * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 + * 13.6.2.7.2 RGB interface + * both claim "Vsync, Hsync, and VDEN are active high signals.", the + * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. + */ + if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { + adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + } + + return 0; +} + static void exynos_dsi_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) @@ -1488,6 +1515,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable, .atomic_disable = exynos_dsi_atomic_disable,