From patchwork Fri Mar 3 14:51:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59AD7C64EC4 for ; Fri, 3 Mar 2023 14:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230157AbjCCOxI (ORCPT ); Fri, 3 Mar 2023 09:53:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230042AbjCCOxG (ORCPT ); Fri, 3 Mar 2023 09:53:06 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C75F7125A1 for ; Fri, 3 Mar 2023 06:53:02 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so2500293pjp.2 for ; Fri, 03 Mar 2023 06:53:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PGJGqhl3LEdXBGmIvlrEtV96J1iyv0EV2tG0O2KrmWU=; b=kxNMkEPNA5uTQt12iqEOJg13gWNjBO+njH9UPKq9q+Njch5fny+QOmxWEmw0OD9VSL 21tEJ4qCn6sGqctt4UrJNO7sMLERoQ1daNdT2FOc9gfo/gNMxdfpiRoqRAKERfCj1GRI O7aEVl7oSIm3BiUmB3pTM4IBJ9z+6J5FGsBNg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PGJGqhl3LEdXBGmIvlrEtV96J1iyv0EV2tG0O2KrmWU=; b=ePXs0XiPCaDX6yi5wzvHu7Rk2CZcIao+gqsB9O4DTqQAQ9UpO9JdOPKwMEsp6G4Hyp 0fGmfCqXSrZdrb2aepJHR57BjBqz6ieCp/H9oeRK0i2wgXjzK1G8wUCwU+LcMscDduWM F9JKmKVPcvfWmlbt96SPAJ/7QpL/DoEeYFif4FIDaIO+hh60ETnB3NT85WLskdHm+aA8 QnoJzrqhmAMx/TKMPOKVvjzCpxu1uvp5NKyZnDKGJg/L5F7OETODW6A/6iFqJ0NM/ErP yVD8r4HHCFN7abTDNQ2KO+GsC59BOaz3g13VXx37/jivbkS57TtJDnn7C2d4sM6J1E68 tI0w== X-Gm-Message-State: AO0yUKWehf/BIE/HN5THfT65td3ZqNYp6zqszI6lJHXlOmI80JhBxWy/ OEJtp1EcmG4yCBlVJ+ZziL5JpA== X-Google-Smtp-Source: AK7set9WDLXiSi5TxhtHWFtZJtDNDWU6UcRgIgpxL5HD/7NPVSUSwjYyaVO7XhQv9A5q3/H67f0pHg== X-Received: by 2002:a05:6a20:394e:b0:bc:333f:b958 with SMTP id r14-20020a056a20394e00b000bc333fb958mr2791368pzg.30.1677855182228; Fri, 03 Mar 2023 06:53:02 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:53:01 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 09/16] drm: exynos: dsi: Add atomic_get_input_bus_fmts Date: Fri, 3 Mar 2023 20:21:31 +0530 Message-Id: <20230303145138.29233-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Finding the right input bus format throughout the pipeline is hard so add atomic_get_input_bus_fmts callback and initialize with the proper input format from list of supported output formats. This format can be used in pipeline for negotiating bus format between the DSI-end of this bridge and the other component closer to pipeline components. List of Pixel formats are taken from, AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 3.7.4 Pixel formats Table 14. DSI pixel packing formats Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v15: - collect RB from Marek Changes for v12: - update the logic suggested by Marek Changes for v11: - collect RB from Frieder - drop extra line Changes for v10: - none Changes for v9: - added MEDIA_BUS_FMT_FIXED - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt list is unsupported. - added MEDIA_BUS_FMT_YUYV10_1X20, MEDIA_BUS_FMT_YUYV12_1X24 Changes for v8: - added pixel formats supported by NXP AN13573 i.MX 8/RT MIPI DSI/CSI-2 Changes for v7 - v4: - none Changes for v3: - include media-bus-format.h Changes for v2: - none Changes for v1: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 5d971b607e1a..c8829f33f36e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1466,6 +1467,66 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +/* + * This pixel output formats list referenced from, + * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 + * 3.7.4 Pixel formats + * Table 14. DSI pixel packing formats + */ +static const u32 exynos_dsi_pixel_output_fmts[] = { + MEDIA_BUS_FMT_YUYV10_1X20, + MEDIA_BUS_FMT_YUYV12_1X24, + MEDIA_BUS_FMT_UYVY8_1X16, + MEDIA_BUS_FMT_RGB101010_1X30, + MEDIA_BUS_FMT_RGB121212_1X36, + MEDIA_BUS_FMT_RGB565_1X16, + MEDIA_BUS_FMT_RGB666_1X18, + MEDIA_BUS_FMT_RGB888_1X24, +}; + +static bool exynos_dsi_pixel_output_fmt_supported(u32 fmt) +{ + int i; + + if (fmt == MEDIA_BUS_FMT_FIXED) + return false; + + for (i = 0; i < ARRAY_SIZE(exynos_dsi_pixel_output_fmts); i++) { + if (exynos_dsi_pixel_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +exynos_dsi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + if (!exynos_dsi_pixel_output_fmt_supported(output_fmt)) + /* + * Some bridge/display drivers are still not able to pass the + * correct format, so handle those pipelines by falling back + * to the default format till the supported formats finalized. + */ + output_fmt = MEDIA_BUS_FMT_RGB888_1X24; + + input_fmts[0] = output_fmt; + *num_input_fmts = 1; + + return input_fmts; +} + static int exynos_dsi_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, @@ -1514,6 +1575,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_get_input_bus_fmts = exynos_dsi_atomic_get_input_bus_fmts, .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable,