| Message ID | 20231228125805.661725-11-tudor.ambarus@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | e58513b2ff78c70805d3bd7d96bfd76576d4c9e3 |
| Headers | show |
| Series | GS101 Oriole: CMU_PERIC0 support and USI updates | expand |
Hi Tudor, On Thu, 2023-12-28 at 12:58 +0000, Tudor Ambarus wrote: > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > [...] > @@ -380,7 +373,8 @@ serial_0: serial@10a00000 { > reg = <0x10a00000 0xc0>; > interrupts = <GIC_SPI 634 > IRQ_TYPE_LEVEL_HIGH 0>; > - clocks = <&dummy_clk 0>, <&dummy_clk 0>; > + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, > + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; I suspect these two should be the other way around, given the clock-names below? > clock-names = "uart", "clk_uart_baud0"; > samsung,uart-fifosize = <256>; > status = "disabled"; Cheers, A.
On 12/28/23 14:22, André Draszik wrote: > Hi Tudor, Hi, Andre'! > > On Thu, 2023-12-28 at 12:58 +0000, Tudor Ambarus wrote: >> >> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> [...] >> @@ -380,7 +373,8 @@ serial_0: serial@10a00000 { >> reg = <0x10a00000 0xc0>; >> interrupts = <GIC_SPI 634 >> IRQ_TYPE_LEVEL_HIGH 0>; >> - clocks = <&dummy_clk 0>, <&dummy_clk 0>; >> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, >> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; > > I suspect these two should be the other way around, given the clock-names below? These ones look sane to me. The clocks on the USI parent as well. USI datasheet says that IPCLK is the protocol operating clock and PCLK the APB clock. In the serial driver clk_uart_baud0 (IPCLK) is used as the operating clock, all fine here. Tell if you still think otherwise. Thanks! ta > >> clock-names = "uart", "clk_uart_baud0"; >> samsung,uart-fifosize = <256>; >> status = "disabled"; > > Cheers, > A.
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index c693791ae584..0e5b1b490b0b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -180,14 +180,6 @@ HERA_CPU_SLEEP: cpu-hera-sleep { }; }; - /* TODO replace with CCF clock */ - dummy_clk: clock-3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12345>; - clock-output-names = "pclk"; - }; - /* ect node is required to be present by bootloader */ ect { }; @@ -369,7 +361,8 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&dummy_clk>, <&dummy_clk>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; samsung,mode = <USI_V2_UART>; @@ -380,7 +373,8 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&dummy_clk 0>, <&dummy_clk 0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled";
Get rid of the dummy clock and start using the cmu_peric0 clocks for the usi_uart and serial_0 nodes. Tested the serial at 115200, 1000000 and 3000000 baudrates, everthing went fine. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- v2: identify and use gate clocks instead of divider clocks arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-)