| Message ID | 20231228125805.661725-9-tudor.ambarus@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | daff9d192892ea583284eb116a07e8e0086f0e76 |
| Headers | show |
| Series | GS101 Oriole: CMU_PERIC0 support and USI updates | expand |
Hi Tudor, On Thu, 28 Dec 2023 at 12:58, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > Remove the reg-io-width property in order to comply with the bindings. > > The entire bus (PERIC) on which the GS101 serial resides only allows > 32-bit register accesses. The reg-io-width dt property is disallowed > for the "google,gs101-uart" compatible and instead the iotype is > inferred from the compatible. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9747cb3fa03a..2c27c3cb9237 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -366,7 +366,6 @@ usi_uart: usi@10a000c0 { serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - reg-io-width = <4>; interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&dummy_clk 0>, <&dummy_clk 0>;
Remove the reg-io-width property in order to comply with the bindings. The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- v2: new patch arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 - 1 file changed, 1 deletion(-)