@@ -132,6 +132,7 @@ struct s3c64xx_spi_dma_data {
* @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
* @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
* @clk_div: Internal clock divider
+ * @fifosize: size of the FIFO
* @quirks: Bitmask of known quirks
* @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
* @clk_from_cmu: True, if the controller does not include a clock mux and
@@ -150,6 +151,7 @@ struct s3c64xx_spi_port_config {
int tx_st_done;
int quirks;
int clk_div;
+ unsigned int fifosize;
bool high_speed;
bool clk_from_cmu;
bool clk_ioclk;
@@ -176,6 +178,7 @@ struct s3c64xx_spi_port_config {
* @tx_dma: Local transmit DMA data (e.g. chan and direction)
* @port_conf: Local SPI port configuration data
* @port_id: Port identification number
+ * @fifosize: size of the FIFO
*/
struct s3c64xx_spi_driver_data {
void __iomem *regs;
@@ -195,6 +198,7 @@ struct s3c64xx_spi_driver_data {
struct s3c64xx_spi_dma_data tx_dma;
const struct s3c64xx_spi_port_config *port_conf;
unsigned int port_id;
+ unsigned int fifosize;
};
static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
@@ -404,7 +408,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
if (sdd->rx_dma.ch && sdd->tx_dma.ch)
- return xfer->len > FIFO_DEPTH(sdd);
+ return xfer->len > sdd->fifosize;
return false;
}
@@ -702,7 +706,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host,
struct spi_transfer *xfer)
{
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
- const unsigned int fifo_len = FIFO_DEPTH(sdd);
+ const unsigned int fifo_len = sdd->fifosize;
const void *tx_buf = NULL;
void *rx_buf = NULL;
int target_len = 0, origin_len = 0;
@@ -1154,6 +1158,11 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
sdd->port_id = pdev->id;
}
+ if (sdd->port_conf->fifosize)
+ sdd->fifosize = sdd->port_conf->fifosize;
+ else
+ sdd->fifosize = FIFO_DEPTH(sdd);
+
sdd->cur_bpw = 8;
sdd->tx_dma.direction = DMA_MEM_TO_DEV;
@@ -1243,7 +1252,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n",
sdd->port_id, host->num_chipselect);
dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
- mem_res, FIFO_DEPTH(sdd));
+ mem_res, sdd->fifosize);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
The IP supports FIFO sizes from 8 to 256 bytes. The SoC that uses the IP dictates the FIFO depth configuration. Add support for inferring the FIFO size from the compatible for those SoCs that use the same FIFO depth across all the instances of the SPI IP. Parsing of a device tree property to determine the FIFO size for the SoCs that use different FIFO sizes for different instances of the SPI IP will be added in a further patch. The scope of this patch is to break the dependency chain between the device tree SPI alias, the fifo_lvl_mask value and the FIFO size from the driver. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/spi/spi-s3c64xx.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)