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AJvYcCXuUZovLjkGsW6uRJlhiQAjH3y9dxZsBLAXlV7EdEEfL3o5VRLDy/WL3bShxACJInxeqduDkCQQFQNxunN73fh0Q8PwkyEReK8eFldO34/6fCA= X-Gm-Message-State: AOJu0YwyAuiRWbeXgyvextq7wQI/GRtNYUl1raKwoOjPBFmQNPVUfJFu UqQpxR8WTUDNtP9il6D3w6enWBNR9wtoeL81HWPub+piM1Yd3eUNcw8tFqQFzmw= X-Google-Smtp-Source: AGHT+IE1KcSWtq0AtIR6tJqtMgKw1sNq7p9OsCBJVxmziFYXd9baY73voLcHuEo5/99B79vRXGQPWg== X-Received: by 2002:a5d:4589:0:b0:33e:c528:c900 with SMTP id p9-20020a5d4589000000b0033ec528c900mr2144866wrq.55.1712233603079; Thu, 04 Apr 2024 05:26:43 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([148.252.128.204]) by smtp.gmail.com with ESMTPSA id bu14-20020a056000078e00b003434b41c83fsm12106303wrb.81.2024.04.04.05.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Apr 2024 05:26:41 -0700 (PDT) From: Peter Griffin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, jejb@linux.ibm.com, martin.petersen@oracle.com, chanho61.park@samsung.com, ebiggers@kernel.org Cc: linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, Peter Griffin Subject: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller Date: Thu, 4 Apr 2024 13:25:47 +0100 Message-ID: <20240404122559.898930-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.478.gd926399ef9-goog In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org> References: <20240404122559.898930-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin Reviewed-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index eddb6b326fde..38ac4fb1397e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 { interrupts = ; }; + cmu_hsi2: clock-controller@14400000 { + compatible = "google,gs101-cmu-hsi2"; + reg = <0x14400000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;