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AJvYcCWZmY/ka1clnmjJb6gyO5QUE28ror+FyOwk5Zj5Bnds3YV18j4rTr7isIRjGkXEAvB8EyqUoXArcBBuasAkoCG8hbGhZ1TPl/0GuQh+WsyDylU= X-Gm-Message-State: AOJu0Ywb9zWq5rP71Ci3tidpYSgLgTAWkqGthVLqSFce+bzjmie3bwFO 4VQGE/g/gzAWrJm13ded8c/p0I1LzebLnbUpb9t/LpzJtpD4LQk6fwJLmccCdXM= X-Google-Smtp-Source: AGHT+IFm+sPiQDs7FxsoddzmGcb5i4tZc2v1N/h+hnpqJdNZnJd4NgTvZqKCbojGXOgRYrkPQiVqiQ== X-Received: by 2002:a5d:47a3:0:b0:346:41a7:2fc2 with SMTP id 3-20020a5d47a3000000b0034641a72fc2mr2953583wrb.32.1714138713599; Fri, 26 Apr 2024 06:38:33 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:63cc:9bae:f542:50e4]) by smtp.gmail.com with ESMTPSA id p3-20020a5d6383000000b00341b451a31asm22327689wru.36.2024.04.26.06.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:38:33 -0700 (PDT) From: Peter Griffin To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin Subject: [PATCH v3 3/4] arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes Date: Fri, 26 Apr 2024 14:38:23 +0100 Message-ID: <20240426133824.2283144-4-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240426133824.2283144-1-peter.griffin@linaro.org> References: <20240426133824.2283144-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin Acked-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 09044deede63..4679ca33c6a0 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1277,6 +1277,42 @@ pinctrl_hsi2: pinctrl@14440000 { interrupts = ; }; + ufs_0_phy: phy@17e04000 { + compatible = "google,gs101-ufs-phy"; + reg = <0x14704000 0x3000>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&ext_24_5m>; + clock-names = "ref_clk"; + status = "disabled"; + }; + + ufs_0: ufs@14700000 { + compatible = "google,gs101-ufs"; + reg = <0x14700000 0x200>, + <0x14701100 0x200>, + <0x14780000 0xa000>, + <0x14600000 0x100>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = ; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + clock-names = "core_clk", "sclk_unipro_main", "fmp", + "aclk", "pclk", "sysreg"; + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + pinctrl-names = "default"; + phys = <&ufs_0_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&sysreg_hsi2 0x710>; + status = "disabled"; + }; + cmu_apm: clock-controller@17400000 { compatible = "google,gs101-cmu-apm"; reg = <0x17400000 0x8000>;