Message ID | 20240429-hsi0-gs101-v3-2-f233be0a2455@linaro.org (mailing list archive) |
---|---|
State | Accepted |
Headers | show |
Series | HSI2 support for Google Tensor gs101 | expand |
On Mon, 29 Apr 2024 14:02:18 +0100, André Draszik wrote: > Enable the cmu_hsi2 clock management unit. It feeds some of > the high speed interfaces such as PCIe and UFS. > > Applied, thanks! [2/3] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller https://git.kernel.org/krzk/linux/c/86124c76683e31033180f1d31e7543863ce6d850 Best regards,
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9755a0bb70a1..a0305555c4fd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1267,6 +1267,18 @@ pinctrl_hsi1: pinctrl@11840000 { interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; }; + cmu_hsi2: clock-controller@14400000 { + compatible = "google,gs101-cmu-hsi2"; + reg = <0x14400000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;