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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id dk21-20020a170907941500b00a55aee4bf74sm10981024ejc.79.2024.04.30.02.49.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 02:49:48 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 30 Apr 2024 10:49:48 +0100 Subject: [PATCH v2 3/4] arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-samsung-pinctrl-busclock-dts-v2-3-14fc988139dd@linaro.org> References: <20240430-samsung-pinctrl-busclock-dts-v2-0-14fc988139dd@linaro.org> In-Reply-To: <20240430-samsung-pinctrl-busclock-dts-v2-0-14fc988139dd@linaro.org> To: Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Will McVicker , Sam Protsenko , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Draszik?= X-Mailer: b4 0.12.4 This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 8d4216cbab2e..f8fcbbb06e7b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1327,6 +1327,8 @@ cmu_hsi2: clock-controller@14400000 { pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; + clock-names = "pclk"; interrupts = ; };