| Message ID | 20240503151129.3901815-10-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | b8a4cdbb01312ac72e189072a1058f7948c07f9e |
| Headers | show |
| Series | improve Analogix DP AUX channel handling | expand |
On Fri, May 3, 2024 at 5:13 PM Lucas Stach <l.stach@pengutronix.de> wrote: > > This check is way too late in the DP enable flow. The PLL must be locked > much earlier, before any link training can happen. If the PLL is unlocked > at that point in time there is something seriously wrong in the enable flow. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 5 ----- > 1 file changed, 5 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > index fdb2c2a2b69a..b4a47311cfe8 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > @@ -720,11 +720,6 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp) > > analogix_dp_set_video_color_format(dp); > > - if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { > - dev_err(dp->dev, "PLL is not locked yet.\n"); > - return -EINVAL; > - } > - > for (;;) { > timeout_loop++; > if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) > -- > 2.39.2 > Reviewed-by: Robet Foss <rfoss@kernel.org>
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index fdb2c2a2b69a..b4a47311cfe8 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -720,11 +720,6 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp) analogix_dp_set_video_color_format(dp); - if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { - dev_err(dp->dev, "PLL is not locked yet.\n"); - return -EINVAL; - } - for (;;) { timeout_loop++; if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
This check is way too late in the DP enable flow. The PLL must be locked much earlier, before any link training can happen. If the PLL is unlocked at that point in time there is something seriously wrong in the enable flow. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 5 ----- 1 file changed, 5 deletions(-)