| Message ID | 20241020174825.375096-3-ivo.ivanov.ivanov1@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | a794e783ebf94c7bd9c8d40e390a54fa4322b2cb |
| Headers | show |
| Series | clk: samsung: Introduce Exynos8895 clock driver | expand |
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index cca3e6309..be6b51694 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1370,6 +1370,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, break; case pll_1417x: case pll_1418x: + case pll_1051x: + case pll_1052x: case pll_0818x: case pll_0822x: case pll_0516x: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 3481941ba..858ab367e 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -43,6 +43,8 @@ enum samsung_pll_type { pll_0517x, pll_0518x, pll_531x, + pll_1051x, + pll_1052x, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
These plls are found in the Exynos8895 SoC: - pll1051x: Integer PLL with middle frequency - pll1052x: Integer PLL with low frequency The PLLs are similar enough to pll_0822x, so the same code can handle all. Locktime for 1051x, 1052x is 150 - the same as the pll_0822x lock factor. MDIV, SDIV, PDIV masks and bit shifts are also the same as 0822x. When defining a PLL, the "con" parameter should be set to CON0 register, like this: PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- drivers/clk/samsung/clk-pll.c | 2 ++ drivers/clk/samsung/clk-pll.h | 2 ++ 2 files changed, 4 insertions(+)