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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:58 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/6] arm64: dts: exynos8895: Add Multi Core Timer (MCT) node Date: Sun, 20 Oct 2024 21:21:19 +0300 Message-ID: <20241020182121.377969-5-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index 802e135c4..c95e4713a 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -169,6 +169,26 @@ cmu_peris: clock-controller@10010000 { clock-names = "oscclk", "bus"; }; + timer@10040000 { + compatible = "samsung,exynos8895-mct", + "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + gic: interrupt-controller@10201000 { compatible = "arm,gic-400"; reg = <0x10201000 0x1000>,