Message ID | 20241127-gs101-phy-lanes-orientation-dts-v1-4-5222d8508b71@linaro.org (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Google Pixel 6 (oriole): TCPCI enablement & USB updates | expand |
On Wed, 2024-11-27 at 11:01 +0000, André Draszik wrote: > This is required for the DWC3 core to reliably detect the connected > phy's Vbus state. > > Signed-off-by: André Draszik <andre.draszik@linaro.org> > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index 18d4e7852a1a..ab016fe9b99a 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -1302,6 +1302,7 @@ usbdrd31_dwc3: usb@0 { > interrupts = <GIC_SPI 463 > IRQ_TYPE_LEVEL_HIGH 0>; > phys = <&usbdrd31_phy 0>, <&usbdrd31_phy > 1>; > phy-names = "usb2-phy", "usb3-phy"; > + snps,dis_rxdet_inp3_quirk; Seems this alone isn't enough in all cases, I'll send an update in a while. Cheers, Andre'
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 18d4e7852a1a..ab016fe9b99a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1302,6 +1302,7 @@ usbdrd31_dwc3: usb@0 { interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis_rxdet_inp3_quirk; status = "disabled"; }; };
This is required for the DWC3 core to reliably detect the connected phy's Vbus state. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+)