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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa69448304asm276347066b.45.2024.12.10.10.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 10:02:22 -0800 (PST) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] arm64: dts: exynos8895: Add syscon-poweroff and syscon-reboot nodes Date: Tue, 10 Dec 2024 20:02:16 +0200 Message-ID: <20241210180216.398165-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241210180216.398165-1-ivo.ivanov.ivanov1@gmail.com> References: <20241210180216.398165-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For Exynos8895, a reboot is handled by setting the bit(SWRESET_SYSTEM[1]) of SWRESET register(PMU + 0x400) and power-off is handled by setting bit(DATA[8]) of PS_HOLD_CONTROL register (PMU + 0x330c). Tested using "reboot" and "poweroff -p" commands. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index 90b318b2f..9eb89dd19 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -388,6 +388,21 @@ pmu_system_controller: system-controller@16480000 { compatible = "samsung,exynos8895-pmu", "samsung,exynos7-pmu", "syscon"; reg = <0x16480000 0x10000>; + + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_system_controller>; + offset = <0x330c>; /* PS_HOLD_CONTROL */ + mask = <0x100>; /* reset value */ + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x400>; /* SWRESET */ + mask = <0x1>; /* SWRESET_SYSTEM */ + value = <0x1>; /* reset value */ + }; }; pinctrl_alive: pinctrl@164b0000 {