@@ -1586,6 +1586,20 @@ static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
};
+static const struct s3c64xx_spi_port_config exynos990_spi_port_config = {
+ /* fifo-depth must be specified in the device tree. */
+ .fifo_depth = 0,
+ .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2,
+ .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2,
+ .tx_st_done = 25,
+ .clk_div = 4,
+ .high_speed = true,
+ .clk_from_cmu = true,
+ .has_loopback = true,
+ .use_32bit_io = true,
+ .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
+};
+
static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
.fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
@@ -1664,6 +1678,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
{ .compatible = "samsung,exynos850-spi",
.data = &exynos850_spi_port_config,
},
+ { .compatible = "samsung,exynos990-spi",
+ .data = &exynos990_spi_port_config,
+ },
{ .compatible = "samsung,exynosautov9-spi",
.data = &exynosautov9_spi_port_config,
},
Exynos990 uses the same version of USI SPI (v2.1) as the GS101. Removed fifo_lvl_mask and rx_lvl_offset, and changed to the new data configuration port. The difference from other new port configuration data is that fifo_depth is only specified in fifo-depth in DT. Exynos 990 data for SPI: - The depth of the FIFO is not the same size on all nodes. A depth of 64 bytes is used on most nodes, while a depth of 256 bytes is used on 3 specific nodes (SPI 8/9/10). - The Exynos 990 only allows access to 32-bit registers. If access is attempted with a different size, an error interrupt is generated. Therefore, it is necessary to perform write accesses to registers in 32-bit blocks. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> --- drivers/spi/spi-s3c64xx.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)