From patchwork Tue Oct 31 12:32:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 10034419 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 47040602B9 for ; Tue, 31 Oct 2017 12:34:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B456288A2 for ; Tue, 31 Oct 2017 12:34:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1B88327B81; Tue, 31 Oct 2017 12:34:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_HI,RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 790FE28A20 for ; Tue, 31 Oct 2017 12:34:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932744AbdJaMeD (ORCPT ); Tue, 31 Oct 2017 08:34:03 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:43642 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932724AbdJaMd7 (ORCPT ); Tue, 31 Oct 2017 08:33:59 -0400 Received: by mail-qt0-f193.google.com with SMTP id j58so20461865qtj.0 for ; Tue, 31 Oct 2017 05:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WWz94ayGh6yJVRSOWE1uPdZjJJVChUZ3Pa+t/HhNBfQ=; b=XCufL3BeGmtdYJtdMgYZ23m87jRCbX9TUY3yZ7RbERWIdmdpYRZpfKnt6sWBSmb2nL E9DgwhPmDM+9gRc9bLrfKZib12zYONSFYXfTaJiFWA2LJEbOOaz+BVt3l+AY2Nh048bb s+gIPWNC3918KVNKGMtWRHdj6tfDaoLxenqDc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WWz94ayGh6yJVRSOWE1uPdZjJJVChUZ3Pa+t/HhNBfQ=; b=BTg3OwUKkzwuxXi838uX9POZa2ybswYyJvPDC1SB4KD6Pe/omWqIGf34D4CbXkWosc 7nNqVSui5LrySK6dLhfinm+JlHRHiEhG/4PQ1MJ6gCYJa2bN5jrnWmG91kcNXdIlFwDq bwDoi5cedJcMWeaIjMLZ8wdnp90dySCGaymfqBWEHZ1VoIrF6IvAbGAVVJG/hqdibV8l Y+hsf+5RCbYjQW6VXENBWXC9Y8nW/imbjz3a/6KsAFkhgJ2RZT1c3GabPDG6RcOjjN9i LRdf1Jyi+Ek4Ed52eethYM7xyCwDbqTLzeY2cz0HV1BrLHbp4EFzrO8BKgZr8jF2REV5 rJtQ== X-Gm-Message-State: AMCzsaXqohGdhQsINJUzr4TTH6Y/IzEotLWyaVKSE9VoD2WNdDZ73+GD RP9qTt15qr7cHyO4sQuFF3HHr9Pl X-Google-Smtp-Source: ABhQp+TgDPRcV60xUxs4hw4y9YKy9Z1G8i/pFgWK7il/3XGRUioUjX7Kv61trr++g18nC5YfQTh9gQ== X-Received: by 10.200.8.78 with SMTP id x14mr2523950qth.316.1509453238715; Tue, 31 Oct 2017 05:33:58 -0700 (PDT) Received: from host1.dhcp.avagotech.net ([192.19.239.250]) by smtp.gmail.com with ESMTPSA id p31sm790811qtj.12.2017.10.31.05.33.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 Oct 2017 05:33:58 -0700 (PDT) From: Suganath Prabu S To: linux-scsi@vger.kernel.org Cc: Sathya.Prakash@broadcom.com, linux-kernel@vger.kernel.org, sreekanth.reddy@broadcom.com, linux-nvme@lists.infradead.org, Suganath Prabu S , Chaitra P B Subject: [PATCH 12/13] mpt3sas: Fix sparse warnings Date: Tue, 31 Oct 2017 18:02:38 +0530 Message-Id: <1509453159-7028-13-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 2.0.2 In-Reply-To: <1509453159-7028-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1509453159-7028-1-git-send-email-suganath-prabu.subramani@broadcom.com> MIME-Version: 1.0 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 1) Used variable __le64/__le32 whichever required in building NVME PRP, and passed to LE Controller. 2) Remove unused functions, And Declared functions as static which are used only in mpt3sas_scsih.c. Signed-off-by: Chaitra P B Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 22 ++++++++++----------- drivers/scsi/mpt3sas/mpt3sas_scsih.c | 37 +++++------------------------------- 2 files changed, 16 insertions(+), 43 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 0da639d..3061c17 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -1437,8 +1437,8 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, size_t data_in_sz) { int prp_size = NVME_PRP_SIZE; - u64 *prp_entry, *prp1_entry, *prp2_entry, *prp_entry_phys; - u64 *prp_page, *prp_page_phys; + __le64 *prp_entry, *prp1_entry, *prp2_entry, *prp_entry_phys; + __le64 *prp_page, *prp_page_phys; u32 offset, entry_len; u32 page_mask_result, page_mask; dma_addr_t paddr; @@ -1455,17 +1455,17 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * PRP1 is located at a 24 byte offset from the start of the NVMe * command. Then set the current PRP entry pointer to PRP1. */ - prp1_entry = (u64 *)(nvme_encap_request->NVMe_Command + + prp1_entry = (__le64 *)(nvme_encap_request->NVMe_Command + NVME_CMD_PRP1_OFFSET); - prp2_entry = (u64 *)(nvme_encap_request->NVMe_Command + + prp2_entry = (__le64 *)(nvme_encap_request->NVMe_Command + NVME_CMD_PRP2_OFFSET); prp_entry = prp1_entry; /* * For the PRP entries, use the specially allocated buffer of * contiguous memory. */ - prp_page = (u64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); - prp_page_phys = (u64 *)mpt3sas_base_get_pcie_sgl_dma(ioc, smid); + prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); + prp_page_phys = (__le64 *)mpt3sas_base_get_pcie_sgl_dma(ioc, smid); /* * Check if we are within 1 entry of a page boundary we don't @@ -1475,8 +1475,8 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask; if (!page_mask_result) { /* Bump up to next page boundary. */ - prp_page = (u64 *)((u8 *)prp_page + prp_size); - prp_page_phys = (u64 *)((u8 *)prp_page_phys + prp_size); + prp_page = (__le64 *)((u8 *)prp_page + prp_size); + prp_page_phys = (__le64 *)((u8 *)prp_page_phys + prp_size); } /* @@ -1604,7 +1604,7 @@ _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, * Returns: true: PRPs are built * false: IEEE SGLs needs to be built */ -void +static void base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, struct scsi_cmnd *scmd, Mpi25SCSIIORequest_t *mpi_request, @@ -1612,7 +1612,7 @@ base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, { int sge_len, offset, num_prp_in_chain = 0; Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; - u64 *curr_buff; + __le64 *curr_buff; dma_addr_t msg_phys; u64 sge_addr; u32 page_mask, page_mask_result; @@ -1740,7 +1740,7 @@ base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc, struct scatterlist *sg_scmd; bool build_prp = true; - data_length = cpu_to_le32(scsi_bufflen(scmd)); + data_length = scsi_bufflen(scmd); sg_scmd = scsi_sglist(scmd); /* If Datalenth is <= 16K and number of SGE’s entries are <= 2 diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c index 72dd57f..31e9343 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c +++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c @@ -599,7 +599,7 @@ __mpt3sas_get_pdev_from_target(struct MPT3SAS_ADAPTER *ioc, * * This searches for pcie_device from target, then return pcie_device object. */ -struct _pcie_device * +static struct _pcie_device * mpt3sas_get_pdev_from_target(struct MPT3SAS_ADAPTER *ioc, struct MPT3SAS_TARGET *tgt_priv) { @@ -942,7 +942,7 @@ _scsih_sas_device_init_add(struct MPT3SAS_ADAPTER *ioc, } -struct _pcie_device * +static struct _pcie_device * __mpt3sas_get_pdev_by_wwid(struct MPT3SAS_ADAPTER *ioc, u64 wwid) { struct _pcie_device *pcie_device; @@ -975,7 +975,7 @@ found_device: * * This searches for pcie_device based on wwid, then return pcie_device object. */ -struct _pcie_device * +static struct _pcie_device * mpt3sas_get_pdev_by_wwid(struct MPT3SAS_ADAPTER *ioc, u64 wwid) { struct _pcie_device *pcie_device; @@ -989,7 +989,7 @@ mpt3sas_get_pdev_by_wwid(struct MPT3SAS_ADAPTER *ioc, u64 wwid) } -struct _pcie_device * +static struct _pcie_device * __mpt3sas_get_pdev_by_idchannel(struct MPT3SAS_ADAPTER *ioc, int id, int channel) { @@ -1012,34 +1012,7 @@ found_device: return pcie_device; } - -/** - * mpt3sas_get_pdev_by_idchannel - pcie device search - * @ioc: per adapter object - * @id: Target ID - * @channel: Channel ID - * - * Context: This function will acquire ioc->pcie_device_lock and will release - * before returning the pcie_device object. - * - * This searches for pcie_device based on id and channel, then return - * pcie_device object. - */ -struct _pcie_device * -mpt3sas_get_pdev_by_idchannel(struct MPT3SAS_ADAPTER *ioc, int id, int channel) -{ - struct _pcie_device *pcie_device; - unsigned long flags; - - spin_lock_irqsave(&ioc->pcie_device_lock, flags); - pcie_device = __mpt3sas_get_pdev_by_idchannel(ioc, id, channel); - spin_unlock_irqrestore(&ioc->pcie_device_lock, flags); - - return pcie_device; -} - - -struct _pcie_device * +static struct _pcie_device * __mpt3sas_get_pdev_by_handle(struct MPT3SAS_ADAPTER *ioc, u16 handle) { struct _pcie_device *pcie_device;