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Wed, 24 Jan 2018 22:14:08 +0000 Received: from DM5PR2101MB1030.namprd21.prod.outlook.com ([fe80::d5db:a805:a24c:d4bc]) by DM5PR2101MB1030.namprd21.prod.outlook.com ([fe80::d5db:a805:a24c:d4bc%3]) with mapi id 15.20.0464.006; Wed, 24 Jan 2018 22:14:08 +0000 From: "Michael Kelley (EOSG)" To: KY Srinivasan , Stephen Hemminger , "martin.petersen@oracle.com" , "longi@microsoft.com" , "JBottomley@odin.com" , "devel@linuxdriverproject.org" , "linux-kernel@vger.kernel.org" , "linux-scsi@vger.kernel.org" CC: "Michael Kelley (EOSG)" Subject: [PATCH 1/1] scsi: storvsc: Spread interrupts when picking a channel for I/O requests Thread-Topic: [PATCH 1/1] scsi: storvsc: Spread interrupts when picking a channel for I/O requests Thread-Index: AQHTlWCnc+A/Qzvuo0G+StbT1Ra74A== Date: Wed, 24 Jan 2018 22:14:08 +0000 Message-ID: <1516831913-26013-1-git-send-email-mikelley@ntdev.microsoft.com> Reply-To: "Michael Kelley (EOSG)" Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 1.8.3.1 x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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x-microsoft-antispam-message-info: CImD+KUe918XkDxoYYSh5qCqASTAmPejyx5OwCq/p/g5Eh2dFUWpVqpxchAs162AKc5CtPyQFjXova5c4OD4tA== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 48676eb5-2c17-48de-c978-08d56377ca2a X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jan 2018 22:14:08.4821 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB1110 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update the algorithm in storvsc_do_io to look for a channel starting with the current CPU + 1 and wrap around (within the current NUMA node). This spreads VMbus interrupts more evenly across CPUs. Previous code always started with first CPU in the current NUMA node, skewing the interrupt load to that CPU. Signed-off-by: Michael Kelley Reviewed-by: Long Li --- drivers/scsi/storvsc_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c index e07907d..f3264c4 100644 --- a/drivers/scsi/storvsc_drv.c +++ b/drivers/scsi/storvsc_drv.c @@ -1310,7 +1310,8 @@ static int storvsc_do_io(struct hv_device *device, */ cpumask_and(&alloced_mask, &stor_device->alloced_cpus, cpumask_of_node(cpu_to_node(q_num))); - for_each_cpu(tgt_cpu, &alloced_mask) { + for_each_cpu_wrap(tgt_cpu, &alloced_mask, + outgoing_channel->target_cpu + 1) { if (tgt_cpu != outgoing_channel->target_cpu) { outgoing_channel = stor_device->stor_chns[tgt_cpu];