From patchwork Mon Apr 9 10:04:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaitra P B X-Patchwork-Id: 10330945 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5C22F6020F for ; Mon, 9 Apr 2018 10:05:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5554E28897 for ; Mon, 9 Apr 2018 10:05:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 49E6028AE0; Mon, 9 Apr 2018 10:05:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95C6528897 for ; Mon, 9 Apr 2018 10:05:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751767AbeDIKFa (ORCPT ); Mon, 9 Apr 2018 06:05:30 -0400 Received: from mail-qt0-f194.google.com ([209.85.216.194]:33176 "EHLO mail-qt0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751754AbeDIKF3 (ORCPT ); Mon, 9 Apr 2018 06:05:29 -0400 Received: by mail-qt0-f194.google.com with SMTP id d50so8488440qtc.0 for ; Mon, 09 Apr 2018 03:05:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RprNQLuphtOGwFJWc93YsHg+pHGhXl6OXY4oYV5sTKM=; b=Kwq+YcGtydGNmX0JC9M1OXLrNgLcJ+Oy4dv/6wiARlhabz6EaLzum7PSvSPfmB25Nc dcn9zvKGVWKr1eE5t+6I7bJZEX/Yw+slGNJs8gKQrTb6AsRSRGba5TQ9r+o9sG1rtSUG a4e9AoLkxNFHTi2VTerM4qI3nXfqSkj9ES2Xk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RprNQLuphtOGwFJWc93YsHg+pHGhXl6OXY4oYV5sTKM=; b=UV9sRFrvfl0lmESTD7sPumNzMBld2qyNL16y8A4fdRM6/nImiZb42G+9coYxNrQexn N+A1BTuCR237ywoxf/Nw/V0IIGJzikR7p076UR6yAH4D2zCK+DVT0g2tUlG7zftnLmOe SvScdgNIeyCFfy54X4pP4O3GMxlHFcgwJiMdijLtH7bX7hlt9jRR71xF41Mg7cAhgXrE P8BtNaThuHLJSHEuxumD8BEp+TdqvEa7jkhJIfR/JX6bPTJSW3UszBi+mO+lq8P4bzUs gtr+oduReGP37muDu7oLt3EvklXF5MZIdZR+C/tboZOh4corv9YVkeyjBsEnq0Y1Or0f 5k3g== X-Gm-Message-State: ALQs6tAcPiiFYSyAZ5Kzjc6G05fp5imv+aFtYBDVuced280B6L0PkMc9 8AWwJn24woEss2uWbobl2lcAKT/uhzM= X-Google-Smtp-Source: AIpwx4+VwFbdF7midXqxOk84Q8FjclsMD0nbDcLaP0gqOv7JAZ9NXsH1EzDUHFJJwwPsXLl1Gmhn+g== X-Received: by 10.200.68.217 with SMTP id b25mr16696176qto.138.1523268328495; Mon, 09 Apr 2018 03:05:28 -0700 (PDT) Received: from localhost.localdomain.localdomain ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id l52sm13856884qtc.45.2018.04.09.03.05.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Apr 2018 03:05:27 -0700 (PDT) From: Chaitra P B To: linux-scsi@vger.kernel.org Cc: Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, suganath-prabu.subramani@broadcom.com, Chaitra P B Subject: [PATCH v2 04/14] mpt3sas: Optimize I/O memory consumption in driver. Date: Mon, 9 Apr 2018 06:04:51 -0400 Message-Id: <1523268301-14453-5-git-send-email-chaitra.basappa@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1523268301-14453-1-git-send-email-chaitra.basappa@broadcom.com> References: <1523268301-14453-1-git-send-email-chaitra.basappa@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For every IO, memory of PAGE size is allocated for handling NVMe native PRPS. And in addition to that for every IO (chains need per IO * chain buffer size, e.g. 38 * 128byte) amount of memory is allocated for chain buffers. However, at any point of time; the IO request can be for NVMe target device (where PRP's page is used for framing PRP's) or can be for SCSI target device (where chain buffers are used for framing chain SGE's). This patch modifies the driver to reuse same pre-allocated PRP page buffers as a chain buffer for IO's targeted for SCSI target devices. No need to allocate separate buffers for chain SGE's buffers. Suppose if the number of chain buffers need for IO doesn't fit in the PRP Page size then driver maintain's separate buffers for those extra chain buffers that exceeds the PRP page size. For example consider PRP page size as 4K and chain buffer size as 128 bytes, then number of chain buffers that can fit in PRP page is 4096/128 => 32. if the number of chain buffer need per IO exceeds 32; for example consider number of chains need per IO is 36 then for remaining 4 chain buffer's driver allocates them individual. Signed-off-by: Chaitra P B Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 80 +++++++++++++++++++++++-------------- 1 file changed, 51 insertions(+), 29 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 1e8e399..701e1e7 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4188,7 +4188,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) kfree(ioc->internal_lookup); if (ioc->chain_lookup) { for (i = 0; i < ioc->scsiio_depth; i++) { - for (j = 0; j < ioc->chains_needed_per_io; j++) { + for (j = ioc->chains_per_prp_buffer; + j < ioc->chains_needed_per_io; j++) { ct = &ioc->chain_lookup[i].chains_per_smid[j]; if (ct && ct->chain_buffer) dma_pool_free(ioc->chain_dma_pool, @@ -4506,7 +4507,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc->chain_lookup = kzalloc(sz, GFP_KERNEL); if (!ioc->chain_lookup) { pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages " - "failed\n", ioc->name); + "failed\n", ioc->name); goto out; } @@ -4520,33 +4521,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) } } - ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, - ioc->chain_segment_sz, 16, 0); - if (!ioc->chain_dma_pool) { - pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", - ioc->name); - goto out; - } - for (i = 0; i < ioc->scsiio_depth; i++) { - for (j = 0; j < ioc->chains_needed_per_io; j++) { - ct = &ioc->chain_lookup[i].chains_per_smid[j]; - ct->chain_buffer = dma_pool_alloc( - ioc->chain_dma_pool , GFP_KERNEL, - &ct->chain_buffer_dma); - if (!ct->chain_buffer) { - pr_err(MPT3SAS_FMT "chain_lookup: " - " pci_pool_alloc failed\n", ioc->name); - goto out; - } - } - total_sz += ioc->chain_segment_sz; - } - - dinitprintk(ioc, pr_info(MPT3SAS_FMT - "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", - ioc->name, ioc->chain_depth, ioc->chain_segment_sz, - ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); - /* initialize hi-priority queue smid's */ ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, sizeof(struct request_tracker), GFP_KERNEL); @@ -4587,6 +4561,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) * be required for NVMe PRP's, only each set of NVMe blocks will be * contiguous, so a new set is allocated for each possible I/O. */ + ioc->chains_per_prp_buffer = 0; if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { nvme_blocks_needed = (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; @@ -4609,6 +4584,11 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc->name); goto out; } + + ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz; + ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer, + ioc->chains_needed_per_io); + for (i = 0; i < ioc->scsiio_depth; i++) { ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc( ioc->pcie_sgl_dma_pool, GFP_KERNEL, @@ -4619,13 +4599,55 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc->name); goto out; } + for (j = 0; j < ioc->chains_per_prp_buffer; j++) { + ct = &ioc->chain_lookup[i].chains_per_smid[j]; + ct->chain_buffer = + ioc->pcie_sg_lookup[i].pcie_sgl + + (j * ioc->chain_segment_sz); + ct->chain_buffer_dma = + ioc->pcie_sg_lookup[i].pcie_sgl_dma + + (j * ioc->chain_segment_sz); + } } dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), " "element_size(%d), pool_size(%d kB)\n", ioc->name, ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); + dinitprintk(ioc, pr_info(MPT3SAS_FMT "Number of chains can " + "fit in a PRP page(%d)\n", ioc->name, + ioc->chains_per_prp_buffer)); total_sz += sz * ioc->scsiio_depth; } + + ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, + ioc->chain_segment_sz, 16, 0); + if (!ioc->chain_dma_pool) { + pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", + ioc->name); + goto out; + } + for (i = 0; i < ioc->scsiio_depth; i++) { + for (j = ioc->chains_per_prp_buffer; + j < ioc->chains_needed_per_io; j++) { + ct = &ioc->chain_lookup[i].chains_per_smid[j]; + ct->chain_buffer = dma_pool_alloc( + ioc->chain_dma_pool, GFP_KERNEL, + &ct->chain_buffer_dma); + if (!ct->chain_buffer) { + pr_err(MPT3SAS_FMT "chain_lookup: " + " pci_pool_alloc failed\n", ioc->name); + _base_release_memory_pools(ioc); + goto out; + } + } + total_sz += ioc->chain_segment_sz; + } + + dinitprintk(ioc, pr_info(MPT3SAS_FMT + "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", + ioc->name, ioc->chain_depth, ioc->chain_segment_sz, + ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); + /* sense buffers, 4 byte align */ sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,