From patchwork Tue Apr 24 09:28:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaitra P B X-Patchwork-Id: 10359087 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6A86260547 for ; Tue, 24 Apr 2018 09:29:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D24F28D31 for ; Tue, 24 Apr 2018 09:29:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 51C4C28D40; Tue, 24 Apr 2018 09:29:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 807A228D31 for ; Tue, 24 Apr 2018 09:29:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754044AbeDXJ3k (ORCPT ); Tue, 24 Apr 2018 05:29:40 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:42463 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753553AbeDXJ3d (ORCPT ); Tue, 24 Apr 2018 05:29:33 -0400 Received: by mail-qt0-f193.google.com with SMTP id c2-v6so3420308qtn.9 for ; Tue, 24 Apr 2018 02:29:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PzyKqJIFhOzl8D+e9x0QdSMtiVuU4O2vb7UTt7Nz/e4=; b=goTKwdU4T5BD+Iz/i1YO7CR/gNHEcL/BLw+SX3lLEjsXD372WkbtJgNIS9bfDQ6G42 Hil3lHmBvNOLdnFZsdu2pTgWgE1Fk+LdHSNO/FSfJ9Oo4SMgfTbZwGfBePmZOvLf5nMU W0zWwGCGeNc1ol/4y3pdgLEva0jiColmHmAFU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PzyKqJIFhOzl8D+e9x0QdSMtiVuU4O2vb7UTt7Nz/e4=; b=hrtEXb5eQF/FrnQ4fB3kygb5jMF8RDCwdFTWju1/3kHWPgVarC9EbbE7pBZ5Sc4g46 pJIPPdR0iNGGB7uirLFHY4BVSJSjR8y4Uy5q2YcrlxfBxJz+T6pI0c0D3Pq4eI4X6eQf sOkxhAqeQJ2Cz446ghSMTuP9Cp068HEs/lD/hnauPxARk2GoP6lMAV7pD7N9G5TZUBLc KO/+fhPzF76++0D8LVX62xCjMi53+XbAzkYEY4DyVJGXFQJWmMJDqZtUYeTlTcPQqetS EHUXS8g0VTPOpH/j+wmU/km/h1HtTULROCh08nXpaOEhWq7XN5udVTZvUChBwBOQVjzf +0lQ== X-Gm-Message-State: ALQs6tDaQr3izD7pAZy4T9+RMPJpPSY500NUus9+zerPhGHAlRwVW0pU Enq/XIwtB8/cQ7pyxQd08D251J17EZk= X-Google-Smtp-Source: AB8JxZrkIytXDkyMMdzzDi1d7OtefyzIjq4ucgA033VTCbE7d+oYV48o4wPLcrfzKuT1bg85P8oWLQ== X-Received: by 2002:ac8:24d4:: with SMTP id t20-v6mr1155506qtt.30.1524562172699; Tue, 24 Apr 2018 02:29:32 -0700 (PDT) Received: from localhost.localdomain.localdomain ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id 96sm12615184qkx.71.2018.04.24.02.29.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Apr 2018 02:29:32 -0700 (PDT) From: Chaitra P B To: linux-scsi@vger.kernel.org Cc: Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, suganath-prabu.subramani@broadcom.com, Chaitra P B Subject: [PATCH v3 11/14] mpt3sas: Update MPI Headers Date: Tue, 24 Apr 2018 05:28:40 -0400 Message-Id: <1524562123-33229-12-git-send-email-chaitra.basappa@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1524562123-33229-1-git-send-email-chaitra.basappa@broadcom.com> References: <1524562123-33229-1-git-send-email-chaitra.basappa@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update MPI Files to support protocol level reset for NVMe device. Signed-off-by: Chaitra P B Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpi/mpi2.h | 9 ++++++--- drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h | 30 ++++++++++++++++++++++++------ drivers/scsi/mpt3sas/mpi/mpi2_ioc.h | 7 ++++++- 3 files changed, 36 insertions(+), 10 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpi/mpi2.h b/drivers/scsi/mpt3sas/mpi/mpi2.h index b015c30..1e45268 100644 --- a/drivers/scsi/mpt3sas/mpi/mpi2.h +++ b/drivers/scsi/mpt3sas/mpi/mpi2.h @@ -9,7 +9,7 @@ * scatter/gather formats. * Creation Date: June 21, 2006 * - * mpi2.h Version: 02.00.48 + * mpi2.h Version: 02.00.50 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -114,6 +114,8 @@ * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. + * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. + * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. * -------------------------------------------------------------------------- */ @@ -152,8 +154,9 @@ MPI26_VERSION_MINOR) #define MPI2_VERSION_02_06 (0x0206) -/*Unit and Dev versioning for this MPI header set */ -#define MPI2_HEADER_VERSION_UNIT (0x30) + +/* Unit and Dev versioning for this MPI header set */ +#define MPI2_HEADER_VERSION_UNIT (0x32) #define MPI2_HEADER_VERSION_DEV (0x00) #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h b/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h index 0ad88de..5122920 100644 --- a/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h +++ b/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h @@ -7,7 +7,7 @@ * Title: MPI Configuration messages and pages * Creation Date: November 10, 2006 * - * mpi2_cnfg.h Version: 02.00.40 + * mpi2_cnfg.h Version: 02.00.42 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -219,6 +219,18 @@ * Added ChassisSlot field to SAS Enclosure Page 0. * Added ChassisSlot Valid bit (bit 5) to the Flags field * in SAS Enclosure Page 0. + * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and + * MPI26_MFGPAGE_DEVID_SAS3916 defines. + * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. + * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. + * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to + * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. + * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to + * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. + * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. + * Added NOIOB field to PCIe Device Page 2. + * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to + * the Capabilities field of PCIe Device Page 2. * -------------------------------------------------------------------------- */ @@ -556,7 +568,8 @@ typedef struct _MPI2_CONFIG_REPLY { #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) -#define MPI26_MFGPAGE_DEVID_SAS4008 (0x00A1) +#define MPI26_MFGPAGE_DEVID_SAS3816 (0x00A1) +#define MPI26_MFGPAGE_DEVID_SAS3916 (0x00A0) /*Manufacturing Page 0 */ @@ -3864,20 +3877,25 @@ typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 { typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 { MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ U16 DevHandle; /*0x08 */ - U16 Reserved1; /*0x0A */ - U32 MaximumDataTransferSize;/*0x0C */ + U8 ControllerResetTO; /* 0x0A */ + U8 Reserved1; /* 0x0B */ + U32 MaximumDataTransferSize; /*0x0C */ U32 Capabilities; /*0x10 */ - U32 Reserved2; /*0x14 */ + U16 NOIOB; /* 0x14 */ + U16 Reserved2; /* 0x16 */ } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t; -#define MPI26_PCIEDEVICE2_PAGEVERSION (0x00) +#define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) /*defines for PCIe Device Page 2 Capabilities field */ +#define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) +/* Defines for the NOIOB field */ +#define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) /**************************************************************************** * PCIe Link Config Pages (MPI v2.6 and later) diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h b/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h index cc2aff7..1faec3a 100644 --- a/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h +++ b/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h @@ -7,7 +7,7 @@ * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages * Creation Date: October 11, 2006 * - * mpi2_ioc.h Version: 02.00.32 + * mpi2_ioc.h Version: 02.00.34 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -167,6 +167,10 @@ * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP. * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related * defines for the ReasonCode field. + * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD. + * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED + * to the ReasonCode field in PCIe Device Status Change + * Event Data. * -------------------------------------------------------------------------- */ @@ -1182,6 +1186,7 @@ typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE { #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10) +#define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11) /*PCIe Enumeration Event data (MPI v2.6 and later) */