From patchwork Thu May 31 10:34:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaitra P B X-Patchwork-Id: 10440675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9C368602BD for ; Thu, 31 May 2018 10:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C83529223 for ; Thu, 31 May 2018 10:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 804702921A; Thu, 31 May 2018 10:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 160D32921A for ; Thu, 31 May 2018 10:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754527AbeEaKf1 (ORCPT ); Thu, 31 May 2018 06:35:27 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:46497 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754504AbeEaKfY (ORCPT ); Thu, 31 May 2018 06:35:24 -0400 Received: by mail-qt0-f193.google.com with SMTP id h5-v6so19219106qtm.13 for ; Thu, 31 May 2018 03:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FgsXhKggcfkNe1NaqkpqfU6XKiT8cK5fpV+lxV8vov4=; b=eJeyTPJ2m+c/r0CxgWeACCgusunsIA6C29hVl1BMSJ+C9ddqfp/VIi1iqZxm0oWkS9 fclVJLBccF4Br1LpnsYSYOTQSOExsrBHsRCWDu7QfGmIJLqo8+/56BJzTjAmLPpvJj8i MuarJZExYt6b8ICjaTA4AnbeoHF5EKjInGeow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FgsXhKggcfkNe1NaqkpqfU6XKiT8cK5fpV+lxV8vov4=; b=d84zDn/fniNHWcJtuUm+CDKtNMVVCMe9o8e4ELdoxE+e02qupMa2nmtAI1xKXUSDc9 U1kaT6wuIfK18s05HF1fnUrrjIwDnWNtgahLKrhFnUUx4o5kRMi2wWTLCbulEpDuiVUH XQdbt0kC9j5jkKnv8fBy1x+fcGxXCKOTeGnXdWV9ZtvOTnTlB9agxate3qEy1vMRF9Mq 22CTUl3EHofLsWChbIxXWCwB9chbEYMD3F+K6UC61Y8/L8oLldwX4/yooGLNnpSJyoRp GIfR2YybAClQRes+JlJcHtuDnVTFzM24J6UBPRQJlUpsDv3OGf3ZJZkPAqZWEffHdds3 BeEQ== X-Gm-Message-State: APt69E3CuC2fQuE4PBu7IfjGCZRX8ijCtGcHvx6m19vbQcXCHG511gSm NK/IbtXcbIy+BdJL5pEo82ACItjb0jA= X-Google-Smtp-Source: ADUXVKLep7f9CmfIvVa1Wmk0h+Y+99w/E07j7bE3E6IaxLGmxDnY4ieApkUjbDgKpuvmD20wfw50fg== X-Received: by 2002:ac8:201:: with SMTP id k1-v6mr6028411qtg.220.1527762923033; Thu, 31 May 2018 03:35:23 -0700 (PDT) Received: from localhost.localdomain.localdomain ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id n79-v6sm12661343qkn.84.2018.05.31.03.35.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 May 2018 03:35:22 -0700 (PDT) From: Chaitra P B To: linux-scsi@vger.kernel.org Cc: sreekanth.reddy@broadcom.com, suganath-prabu.subramani@broadcom.com, sathya.prakash@broadcom.com, Chaitra P B Subject: [PATCH 5/6] mpt3sas: As per MPI-spec, use combined reply queue for SAS3.5 controllers when HBA supports more than 16 MSI-x vectors. Date: Thu, 31 May 2018 06:34:51 -0400 Message-Id: <1527762892-3204-6-git-send-email-chaitra.basappa@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1527762892-3204-1-git-send-email-chaitra.basappa@broadcom.com> References: <1527762892-3204-1-git-send-email-chaitra.basappa@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Presently driver is using combined reply queue feature when MSI-x vectors > 8, for both SAS3 and SAS3.5 controllers. But as per MPI-spec, 1.For SAS3 controllers, driver should use combined reply queue when HBA supports more than 8 MSI-x vectors. 2.For SAS3.5 controllers, driver should use combined reply queue when HBA supports more than 16 MSI-x vectors. So modified driver code to use combined reply queue for SAS3 controllers when HBA supports > 8 MSI-x vectors and for SAS3.5 controllers when HBA supports > 16 MSI-x vectors. Signed-off-by: Chaitra P B --- drivers/scsi/mpt3sas/mpt3sas_base.c | 15 ++++++++------- drivers/scsi/mpt3sas/mpt3sas_base.h | 1 + 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index cef480a..668f350 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2952,10 +2952,9 @@ mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) _base_free_irq(ioc); _base_disable_msix(ioc); - if (ioc->combined_reply_queue) { - kfree(ioc->replyPostRegisterIndex); - ioc->replyPostRegisterIndex = NULL; - } + kfree(ioc->replyPostRegisterIndex); + ioc->replyPostRegisterIndex = NULL; + if (ioc->chip_phys) { iounmap(ioc->chip); @@ -3062,7 +3061,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) /* Use the Combined reply queue feature only for SAS3 C0 & higher * revision HBAs and also only when reply queue count is greater than 8 */ - if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) { + if (ioc->combined_reply_queue) { /* Determine the Supplemental Reply Post Host Index Registers * Addresse. Supplemental Reply Post Host Index Registers * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and @@ -3086,8 +3085,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); } - } else - ioc->combined_reply_queue = 0; + } if (ioc->is_warpdrive) { ioc->reply_post_host_index[0] = (resource_size_t __iomem *) @@ -5704,6 +5702,9 @@ _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) facts->WhoInit = mpi_reply.WhoInit; facts->NumberOfPorts = mpi_reply.NumberOfPorts; facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; + if (ioc->msix_enable && (facts->MaxMSIxVectors <= + MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc))) + ioc->combined_reply_queue = 0; facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); facts->MaxReplyDescriptorPostQueueDepth = le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index ec222ad..3d49ead 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -323,6 +323,7 @@ * There are twelve Supplemental Reply Post Host Index Registers * and each register is at offset 0x10 bytes from the previous one. */ +#define MAX_COMBINED_MSIX_VECTORS(gen35) ((gen35 == 1) ? 16 : 8) #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3 12 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35 16 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10)