From patchwork Thu Feb 14 05:46:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 10811833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E1421399 for ; Thu, 14 Feb 2019 05:46:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 39E332D37A for ; Thu, 14 Feb 2019 05:46:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2B2FE2D390; Thu, 14 Feb 2019 05:46:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE00E2D37A for ; Thu, 14 Feb 2019 05:46:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392594AbfBNFqj (ORCPT ); Thu, 14 Feb 2019 00:46:39 -0500 Received: from mail-ed1-f65.google.com ([209.85.208.65]:40250 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726129AbfBNFqj (ORCPT ); Thu, 14 Feb 2019 00:46:39 -0500 Received: by mail-ed1-f65.google.com with SMTP id 10so3987597eds.7 for ; Wed, 13 Feb 2019 21:46:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dy+e6oQ7CSinT9QlwhS+fuQA9alIwcaS7YY0JzYje+Q=; b=QE8aFb9LkErgAOO6P40MfZU3n1PBPm/sXyybAePvzs8YCjB1j3BMhs61/slsB+dsOJ JRwEo50wRcs43w/JthFj1CwMg8yI6EJhyDWH84Iie3tQsdDy+WHZbF5jD0SdG3G1PXmz kx9hLbg4SFqTq7qk4maWM/qBvMjtFOxXJ8CsM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dy+e6oQ7CSinT9QlwhS+fuQA9alIwcaS7YY0JzYje+Q=; b=tddHbpAfEnT3dKvbgbA1JxrqwHG9CJ1oFxKiCDiPEMg9mWpM3Y0SLTS7csoLra4NzV klkux/MPBQdfXFIWpenSV14y1/GgwsFXE60Qz3jd6rbr9WETFrSQ8fx5mwTC3YggfBIe soMOcp+B9S/RSw0BvjIsHvRMx4uK3ls1jFENpNEjVn+KYrUkK0FRIuFQyEkbwmzivmH4 2/B1s9IG7oC5Wpt+IKoYm1/0z34+47wUVOpkD90qofOaQ3quMZoC/CVZhkCsM6H2/xPj yuOi9zd5oZU6CiQ4pA5BXr/achZhT33/Rs08djg9T1oaT9X+7mc9sf6mbhBoON+8PC1q qY4w== X-Gm-Message-State: AHQUAuap6gozIthJsRpiG7f/C0MXOU7LoxXFDaCdV7mdkTJ8DrIfKLPe xaYGhnahB3+TCQck9BrTEspY7kMj9/lwxaC9+zR9iPAKfty9meCgXO4xxmDJgO1W9VIY4wKEVY7 nbqzk3DdrhN7GzEeQuSnUdSVVpXLuf3HLDlk8M9aK/nwjEyVAKXCrxa9zLeDQ20Q6FmQWRlk5Dk sozb5w8pXyULMOBrahBlLz X-Google-Smtp-Source: AHgI3IaBYpq++1xVaIRULqh8xli3bF/w2m6vPdJvG/wiExCOk3RuRbmuDJhTQx6LLLeglDdNGDLi3Q== X-Received: by 2002:a17:906:18f1:: with SMTP id e17mr1464025ejf.82.1550123196840; Wed, 13 Feb 2019 21:46:36 -0800 (PST) Received: from dhcp-10-123-20-72.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id h1sm311791ejx.41.2019.02.13.21.46.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Feb 2019 21:46:36 -0800 (PST) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu Subject: [PATCH 4/6] mpt3sas: Load balance to improve performance and avoid soft lockups. Date: Thu, 14 Feb 2019 00:46:09 -0500 Message-Id: <1550123171-15993-5-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1550123171-15993-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1550123171-15993-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Driver uses "reply descriptor post queues" in round robin fashion so that IO's are distributed to all the available reply descriptor post queues equally. With this each reply descriptor post queue load is balanced. This is enabled only if CPUs count to MSI-X vector count ratio is X:1 (where X > 1) This improves performance and also fixes soft lockups. Signed-off-by: Suganath Prabu --- drivers/scsi/mpt3sas/mpt3sas_base.c | 21 +++++++++++++++++++++ drivers/scsi/mpt3sas/mpt3sas_base.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 1f358bc..aadd9e2 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -1382,6 +1382,16 @@ union reply_descriptor { } u; }; +static u32 base_mod64(u64 dividend, u32 divisor) +{ + u32 remainder; + + if (!divisor) + pr_err("mpt3sas: DIVISOR is zero, in div fn\n"); + remainder = do_div(dividend, divisor); + return remainder; +} + /** * _base_process_reply_queue - Process reply descriptors from reply * descriptor post queue. @@ -2845,6 +2855,11 @@ _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) if (!_base_is_controller_msix_enabled(ioc)) return; + ioc->msix_load_balance = false; + if (ioc->reply_queue_count < num_online_cpus()) { + ioc->msix_load_balance = true; + return; + } memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); @@ -3248,6 +3263,12 @@ mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) static inline u8 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) { + /* Enables reply_queue load balancing */ + if (ioc->msix_load_balance) + return ioc->reply_queue_count ? + base_mod64(atomic64_add_return(1, + &ioc->total_io_cnt), ioc->reply_queue_count) : 0; + return ioc->cpu_msix_table[raw_smp_processor_id()]; } diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index fb572cd..3895407 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -1024,6 +1024,9 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc); * @msix_vector_count: number msix vectors * @cpu_msix_table: table for mapping cpus to msix index * @cpu_msix_table_sz: table size + * @total_io_cnt: Gives total IO count, used to load balance the interrupts + * @msix_load_balance: Enables load balancing of interrupts across + * the multiple MSIXs * @schedule_dead_ioc_flush_running_cmds: callback to flush pending commands * @scsi_io_cb_idx: shost generated commands * @tm_cb_idx: task management commands @@ -1200,6 +1203,8 @@ struct MPT3SAS_ADAPTER { u32 ioc_reset_count; MPT3SAS_FLUSH_RUNNING_CMDS schedule_dead_ioc_flush_running_cmds; u32 non_operational_loop; + atomic64_t total_io_cnt; + bool msix_load_balance; /* internal commands, callback index */ u8 scsi_io_cb_idx;