| Message ID | 1579764349-15578-8-git-send-email-cang@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | UFS driver general fixes bundle 4 | expand |
On 1/22/2020 11:25 PM, Can Guo wrote: > After enter hibern8, as UFS JEDEC ver 3.0 requires, a specific gating wait > time is required before disable the device reference clock. If it is not > specified, use the old delay. > > Signed-off-by: Can Guo <cang@codeaurora.org> > --- Reviewed-by: Asutosh Das <asutoshd@codeaurora.org> > drivers/scsi/ufs/ufs-qcom.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c > index 85d7c17..3b5b2d9 100644 > --- a/drivers/scsi/ufs/ufs-qcom.c > +++ b/drivers/scsi/ufs/ufs-qcom.c > @@ -833,6 +833,8 @@ static int ufs_qcom_bus_register(struct ufs_qcom_host *host) > > static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) > { > + unsigned long gating_wait; > + > if (host->dev_ref_clk_ctrl_mmio && > (enable ^ host->is_dev_ref_clk_enabled)) { > u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); > @@ -845,11 +847,16 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) > /* > * If we are here to disable this clock it might be immediately > * after entering into hibern8 in which case we need to make > - * sure that device ref_clk is active at least 1us after the > + * sure that device ref_clk is active for specific time after > * hibern8 enter. > */ > - if (!enable) > - udelay(1); > + if (!enable) { > + gating_wait = host->hba->dev_info.clk_gating_wait_us; > + if (!gating_wait) > + udelay(1); > + else > + usleep_range(gating_wait, gating_wait + 10); > + } > > writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); > >
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index 85d7c17..3b5b2d9 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -833,6 +833,8 @@ static int ufs_qcom_bus_register(struct ufs_qcom_host *host) static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) { + unsigned long gating_wait; + if (host->dev_ref_clk_ctrl_mmio && (enable ^ host->is_dev_ref_clk_enabled)) { u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); @@ -845,11 +847,16 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) /* * If we are here to disable this clock it might be immediately * after entering into hibern8 in which case we need to make - * sure that device ref_clk is active at least 1us after the + * sure that device ref_clk is active for specific time after * hibern8 enter. */ - if (!enable) - udelay(1); + if (!enable) { + gating_wait = host->hba->dev_info.clk_gating_wait_us; + if (!gating_wait) + udelay(1); + else + usleep_range(gating_wait, gating_wait + 10); + } writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
After enter hibern8, as UFS JEDEC ver 3.0 requires, a specific gating wait time is required before disable the device reference clock. If it is not specified, use the old delay. Signed-off-by: Can Guo <cang@codeaurora.org> --- drivers/scsi/ufs/ufs-qcom.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)