diff mbox series

[v7,06/10] dt-bindings: phy: Document Samsung UFS PHY bindings

Message ID 20200426173024.63069-7-alim.akhtar@samsung.com (mailing list archive)
State Superseded
Headers show
Series [v7,01/10] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr | expand

Commit Message

Alim Akhtar April 26, 2020, 5:30 p.m. UTC 
This patch documents Samsung UFS PHY device tree bindings

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
 .../bindings/phy/samsung,ufs-phy.yaml         | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml

Comments

Rob Herring (Arm) May 5, 2020, 3:56 p.m. UTC | #1 
On Sun, Apr 26, 2020 at 11:00:20PM +0530, Alim Akhtar wrote:
> This patch documents Samsung UFS PHY device tree bindings
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
> ---
>  .../bindings/phy/samsung,ufs-phy.yaml         | 74 +++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> new file mode 100644
> index 000000000000..352d5dda320d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SoC series UFS PHY Device Tree Bindings
> +
> +maintainers:
> +  - Alim Akhtar <alim.akhtar@samsung.com>
> +
> +properties:
> +  "#phy-cells":
> +    const: 0
> +
> +  compatible:
> +    enum:
> +      - samsung,exynos7-ufs-phy
> +
> +  reg:
> +    maxItems: 1
> +    description: PHY base register address

Can drop the description. Doesn't add anything special.

> +
> +  reg-names:
> +    items:
> +      - const: phy-pma
> +
> +  clocks:
> +    items:
> +      - description: PLL reference clock
> +      - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
> +      - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
> +      - description: symbol clock for output symbol ( tx0 symbol clock)
> +
> +  clock-names:
> +    items:
> +      - const: ref_clk
> +      - const: rx1_symbol_clk
> +      - const: rx0_symbol_clk
> +      - const: tx0_symbol_clk
> +
> +  samsung,pmu-syscon:
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +    description: phandle for PMU system controller interface, used to
> +                 control pmu registers bits for ufs m-phy
> +
> +required:
> +  - "#phy-cells"
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - samsung,pmu-syscon

Add:

additionalProperties: false

With that,

Reviewed-by: Rob Herring <robh@kernel.org>

> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/exynos7-clk.h>
> +
> +    ufs_phy: ufs-phy@15571800 {
> +        compatible = "samsung,exynos7-ufs-phy";
> +        reg = <0x15571800 0x240>;
> +        reg-names = "phy-pma";
> +        samsung,pmu-syscon = <&pmu_system_controller>;
> +        #phy-cells = <0>;
> +        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
> +                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
> +                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
> +                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
> +        clock-names = "ref_clk", "rx1_symbol_clk",
> +                      "rx0_symbol_clk", "tx0_symbol_clk";
> +
> +    };
> +...
> -- 
> 2.17.1
>
Alim Akhtar May 9, 2020, 12:36 a.m. UTC | #2 
Hi Rob

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 05 May 2020 21:26
> To: Alim Akhtar <alim.akhtar@samsung.com>
> Cc: devicetree@vger.kernel.org; linux-scsi@vger.kernel.org; krzk@kernel.org;
> avri.altman@wdc.com; martin.petersen@oracle.com;
> kwmad.kim@samsung.com; stanley.chu@mediatek.com;
> cang@codeaurora.org; linux-samsung-soc@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v7 06/10] dt-bindings: phy: Document Samsung UFS PHY
> bindings
> 
> On Sun, Apr 26, 2020 at 11:00:20PM +0530, Alim Akhtar wrote:
> > This patch documents Samsung UFS PHY device tree bindings
> >
> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
> > ---
> >  .../bindings/phy/samsung,ufs-phy.yaml         | 74 +++++++++++++++++++
> >  1 file changed, 74 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > new file mode 100644
> > index 000000000000..352d5dda320d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
> > @@ -0,0 +1,74 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
> > +---
> > +$id:
> > +https://protect2.fireeye.com/url?k=5c35df0a-01ffeabd-5c345445-0cc47a3
> > +003e8-
> aa6c980dab2ba33a&q=1&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2F
> > +phy%2Fsamsung%2Cufs-phy.yaml%23
> > +$schema:
> > +https://protect2.fireeye.com/url?k=9734fc5e-cafec9e9-97357711-0cc47a3
> > +003e8-
> 79d176b992774339&q=1&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schem
> > +as%2Fcore.yaml%23
> > +
> > +title: Samsung SoC series UFS PHY Device Tree Bindings
> > +
> > +maintainers:
> > +  - Alim Akhtar <alim.akhtar@samsung.com>
> > +
> > +properties:
> > +  "#phy-cells":
> > +    const: 0
> > +
> > +  compatible:
> > +    enum:
> > +      - samsung,exynos7-ufs-phy
> > +
> > +  reg:
> > +    maxItems: 1
> > +    description: PHY base register address
> 
> Can drop the description. Doesn't add anything special.
> 
> > +
> > +  reg-names:
> > +    items:
> > +      - const: phy-pma
> > +
> > +  clocks:
> > +    items:
> > +      - description: PLL reference clock
> > +      - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
> > +      - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
> > +      - description: symbol clock for output symbol ( tx0 symbol
> > + clock)
> > +
> > +  clock-names:
> > +    items:
> > +      - const: ref_clk
> > +      - const: rx1_symbol_clk
> > +      - const: rx0_symbol_clk
> > +      - const: tx0_symbol_clk
> > +
> > +  samsung,pmu-syscon:
> > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > +    description: phandle for PMU system controller interface, used to
> > +                 control pmu registers bits for ufs m-phy
> > +
> > +required:
> > +  - "#phy-cells"
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - clocks
> > +  - clock-names
> > +  - samsung,pmu-syscon
> 
> Add:
> 
> additionalProperties: false
> 
> With that,
> 
Will update the documentation as per your suggestion

> Reviewed-by: Rob Herring <robh@kernel.org>
>
Thanks for review comments. After fixing, will add your review tag.
 
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/exynos7-clk.h>
> > +
> > +    ufs_phy: ufs-phy@15571800 {
> > +        compatible = "samsung,exynos7-ufs-phy";
> > +        reg = <0x15571800 0x240>;
> > +        reg-names = "phy-pma";
> > +        samsung,pmu-syscon = <&pmu_system_controller>;
> > +        #phy-cells = <0>;
> > +        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
> > +                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
> > +                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
> > +                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
> > +        clock-names = "ref_clk", "rx1_symbol_clk",
> > +                      "rx0_symbol_clk", "tx0_symbol_clk";
> > +
> > +    };
> > +...
> > --
> > 2.17.1
> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index 000000000000..352d5dda320d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,74 @@ 
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+  - Alim Akhtar <alim.akhtar@samsung.com>
+
+properties:
+  "#phy-cells":
+    const: 0
+
+  compatible:
+    enum:
+      - samsung,exynos7-ufs-phy
+
+  reg:
+    maxItems: 1
+    description: PHY base register address
+
+  reg-names:
+    items:
+      - const: phy-pma
+
+  clocks:
+    items:
+      - description: PLL reference clock
+      - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+      - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+      - description: symbol clock for output symbol ( tx0 symbol clock)
+
+  clock-names:
+    items:
+      - const: ref_clk
+      - const: rx1_symbol_clk
+      - const: rx0_symbol_clk
+      - const: tx0_symbol_clk
+
+  samsung,pmu-syscon:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description: phandle for PMU system controller interface, used to
+                 control pmu registers bits for ufs m-phy
+
+required:
+  - "#phy-cells"
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - samsung,pmu-syscon
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos7-clk.h>
+
+    ufs_phy: ufs-phy@15571800 {
+        compatible = "samsung,exynos7-ufs-phy";
+        reg = <0x15571800 0x240>;
+        reg-names = "phy-pma";
+        samsung,pmu-syscon = <&pmu_system_controller>;
+        #phy-cells = <0>;
+        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+        clock-names = "ref_clk", "rx1_symbol_clk",
+                      "rx0_symbol_clk", "tx0_symbol_clk";
+
+    };
+...