@@ -258,6 +258,8 @@ enum device_desc_param {
DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
DEVICE_DESC_PARAM_PSA_TMT = 0x29,
DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
+ DEVICE_DESC_PARAM_HPB_VER = 0x40,
+ DEVICE_DESC_PARAM_HPB_CTRL_MODE = 0x42,
};
/* Interconnect descriptor parameters offsets in bytes*/
@@ -537,6 +539,10 @@ struct ufs_dev_info {
u8 *model;
u16 wspecversion;
u32 clk_gating_wait_us;
+ /* HPB Version */
+ u16 hpb_ver;
+ /* bHPBControl */
+ u8 hpb_control_mode;
};
/**
@@ -6627,6 +6627,17 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
goto out;
}
+ if (desc_buf[DEVICE_DESC_PARAM_UFS_FEAT] & 0x80) {
+ hba->dev_info.hpb_control_mode =
+ desc_buf[DEVICE_DESC_PARAM_HPB_CTRL_MODE];
+ hba->dev_info.hpb_ver =
+ (u16) (desc_buf[DEVICE_DESC_PARAM_HPB_VER] << 8) |
+ desc_buf[DEVICE_DESC_PARAM_HPB_VER + 1];
+ dev_info(hba->dev, "HPB Version: 0x%2x\n",
+ hba->dev_info.hpb_ver);
+ dev_info(hba->dev, "HPB control mode: %d\n",
+ hba->dev_info.hpb_control_mode);
+ }
/*
* getting vendor (manufacturerID) and Bank Index in big endian
* format