From patchwork Mon Jul 6 20:04:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Tangirala X-Patchwork-Id: 11646781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D1D081398 for ; Mon, 6 Jul 2020 20:04:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B74A220715 for ; Mon, 6 Jul 2020 20:04:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="pJ6YvEvM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726478AbgGFUEc (ORCPT ); Mon, 6 Jul 2020 16:04:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725860AbgGFUEc (ORCPT ); Mon, 6 Jul 2020 16:04:32 -0400 Received: from mail-qk1-x74a.google.com (mail-qk1-x74a.google.com [IPv6:2607:f8b0:4864:20::74a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D084C061755 for ; Mon, 6 Jul 2020 13:04:32 -0700 (PDT) Received: by mail-qk1-x74a.google.com with SMTP id a205so26991541qkc.16 for ; Mon, 06 Jul 2020 13:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=dDsmnBvgATw3c4ICMogUEPeEv/n1rzxS+m18yK1F+uM=; b=pJ6YvEvMTwgGeI+kj6tiQpKhxqjkZ0eLMyYauJ6NNIwcJu1Z2Ht4PJMqZAnjJqvCLx xFfFBWxuskdkgRYIojpHYZyjL+F+y92AOmffDauSaYbbQZ/mC+Jq38YJ5UmLySLPzco1 3u6OsA+rcskGFBbZIMnGwVkao11ZfrBLkj9uaUiGLU5a/G8wuzlIsyiYZOzVSsuBptD3 G4LAEDXN/c4e+HV0jPU6Ygu818l3KwOE7tlWZ0NZgA2pO1YL7aqmI17aZ/TTIjNTfyLz XGDRqZ41HoutwoL6HhHwL2fLpXPb30MBKTMVGB2zEsS3nnXRxRfdzIK+HAUJT41QVo+N /CYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=dDsmnBvgATw3c4ICMogUEPeEv/n1rzxS+m18yK1F+uM=; b=K7u+GdE82h/K+dJXDw+XXQcVX9C63HbADmTyGywYGB9P3Q0KqrYcEu2HViGz3x7rJk B/kpGVv2NacaCSZO91hNIYIBc8vm9aysG5kc0r20bD0VylWd7mLUQkeNLIagVrudJwzE Mlmn2bvK+ZU4IHDywIwp8OT8zgdND7CYkgI/aigXKUQT4vdw+0Em//HxPgEluMPTYoIc Jm9hR/fTHsynio6MkBbuVWss6z3aDg6xDBsg4r/PeX1deGiJomwkubHPjbgt+B4hqQ78 EfSI2nXWSFrfB2wfXcxILcpYU1AKqYNc4dDXJLsAk6b5WqLFjOK6SoQgM+du/OQF4eT7 bIeg== X-Gm-Message-State: AOAM532zsyvCtMcrh8rOInF97m22MPavji4JeBz8O6a755xN9eCUJOcm aopHHG2eqJyBlSc4j6I8BrFDzUmmTxGFP84337w30NYRIgwGildPMwBA7zBbWOrKSONo3QNpFhD zCl6E4rUth0beHqXfvoutISse6TEb0cKIxsSHV7EDstNW/hcTA0Pwv/4UzvAt4d5YL2g= X-Google-Smtp-Source: ABdhPJz25uFMOtG25l0gwjx3QWB/ZqcmYaK7e4kWWjRPWvbFMbRYZoiIe62N3Ov38CB+bCKcsTeinuq6Cgo= X-Received: by 2002:a0c:f307:: with SMTP id j7mr24244138qvl.55.1594065871150; Mon, 06 Jul 2020 13:04:31 -0700 (PDT) Date: Mon, 6 Jul 2020 20:04:12 +0000 In-Reply-To: <20200706200414.2027450-1-satyat@google.com> Message-Id: <20200706200414.2027450-2-satyat@google.com> Mime-Version: 1.0 References: <20200706200414.2027450-1-satyat@google.com> X-Mailer: git-send-email 2.27.0.383.g050319c2ae-goog Subject: [PATCH v4 1/3] scsi: ufs: UFS driver v2.1 spec crypto additions From: Satya Tangirala To: linux-scsi@vger.kernel.org, Avri Altman , Alim Akhtar Cc: Barani Muthukumaran , Kuohong Wang , Kim Boojin , Satya Tangirala , Eric Biggers , Stanley Chu Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Add the crypto registers and structs defined in v2.1 of the JEDEC UFSHCI specification in preparation to add support for inline encryption to UFS. Signed-off-by: Satya Tangirala Reviewed-by: Eric Biggers Reviewed-by: Stanley Chu --- drivers/scsi/ufs/ufshcd.c | 3 ++ drivers/scsi/ufs/ufshcd.h | 6 ++++ drivers/scsi/ufs/ufshci.h | 67 +++++++++++++++++++++++++++++++++++++-- 3 files changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index ad4fc829cbb2..4fdb200de46c 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -4792,6 +4792,9 @@ ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) case OCS_MISMATCH_RESP_UPIU_SIZE: case OCS_PEER_COMM_FAILURE: case OCS_FATAL_ERROR: + case OCS_DEVICE_FATAL_ERROR: + case OCS_INVALID_CRYPTO_CONFIG: + case OCS_GENERAL_CRYPTO_ERROR: default: result |= DID_ERROR << 16; dev_err(hba->dev, diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index bf97d616e597..b4981f1c37a2 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -564,6 +564,12 @@ enum ufshcd_caps { * provisioned to be used. This would increase the write performance. */ UFSHCD_CAP_WB_EN = 1 << 7, + + /* + * This capability allows the host controller driver to use the + * inline crypto engine, if it is present + */ + UFSHCD_CAP_CRYPTO = 1 << 8, }; struct ufs_hba_variant_params { diff --git a/drivers/scsi/ufs/ufshci.h b/drivers/scsi/ufs/ufshci.h index c2961d37cc1c..c0651fe6dbbc 100644 --- a/drivers/scsi/ufs/ufshci.h +++ b/drivers/scsi/ufs/ufshci.h @@ -90,6 +90,7 @@ enum { MASK_64_ADDRESSING_SUPPORT = 0x01000000, MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, + MASK_CRYPTO_SUPPORT = 0x10000000, }; #define UFS_MASK(mask, offset) ((mask) << (offset)) @@ -143,6 +144,7 @@ enum { #define DEVICE_FATAL_ERROR 0x800 #define CONTROLLER_FATAL_ERROR 0x10000 #define SYSTEM_BUS_FATAL_ERROR 0x20000 +#define CRYPTO_ENGINE_FATAL_ERROR 0x40000 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ UIC_HIBERNATE_EXIT) @@ -155,11 +157,13 @@ enum { #define UFSHCD_ERROR_MASK (UIC_ERROR |\ DEVICE_FATAL_ERROR |\ CONTROLLER_FATAL_ERROR |\ - SYSTEM_BUS_FATAL_ERROR) + SYSTEM_BUS_FATAL_ERROR |\ + CRYPTO_ENGINE_FATAL_ERROR) #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ CONTROLLER_FATAL_ERROR |\ - SYSTEM_BUS_FATAL_ERROR) + SYSTEM_BUS_FATAL_ERROR |\ + CRYPTO_ENGINE_FATAL_ERROR) /* HCS - Host Controller Status 30h */ #define DEVICE_PRESENT 0x1 @@ -318,6 +322,61 @@ enum { INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, }; +/* CCAP - Crypto Capability 100h */ +union ufs_crypto_capabilities { + __le32 reg_val; + struct { + u8 num_crypto_cap; + u8 config_count; + u8 reserved; + u8 config_array_ptr; + }; +}; + +enum ufs_crypto_key_size { + UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, + UFS_CRYPTO_KEY_SIZE_128 = 0x1, + UFS_CRYPTO_KEY_SIZE_192 = 0x2, + UFS_CRYPTO_KEY_SIZE_256 = 0x3, + UFS_CRYPTO_KEY_SIZE_512 = 0x4, +}; + +enum ufs_crypto_alg { + UFS_CRYPTO_ALG_AES_XTS = 0x0, + UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, + UFS_CRYPTO_ALG_AES_ECB = 0x2, + UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, +}; + +/* x-CRYPTOCAP - Crypto Capability X */ +union ufs_crypto_cap_entry { + __le32 reg_val; + struct { + u8 algorithm_id; + u8 sdus_mask; /* Supported data unit size mask */ + u8 key_size; + u8 reserved; + }; +}; + +#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) +#define UFS_CRYPTO_KEY_MAX_SIZE 64 +/* x-CRYPTOCFG - Crypto Configuration X */ +union ufs_crypto_cfg_entry { + __le32 reg_val[32]; + struct { + u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; + u8 data_unit_size; + u8 crypto_cap_idx; + u8 reserved_1; + u8 config_enable; + u8 reserved_multi_host; + u8 reserved_2; + u8 vsb[2]; + u8 reserved_3[56]; + }; +}; + /* * Request Descriptor Definitions */ @@ -339,6 +398,7 @@ enum { UTP_NATIVE_UFS_COMMAND = 0x10000000, UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, UTP_REQ_DESC_INT_CMD = 0x01000000, + UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000, }; /* UTP Transfer Request Data Direction (DD) */ @@ -358,6 +418,9 @@ enum { OCS_PEER_COMM_FAILURE = 0x5, OCS_ABORTED = 0x6, OCS_FATAL_ERROR = 0x7, + OCS_DEVICE_FATAL_ERROR = 0x8, + OCS_INVALID_CRYPTO_CONFIG = 0x9, + OCS_GENERAL_CRYPTO_ERROR = 0xA, OCS_INVALID_COMMAND_STATUS = 0x0F, MASK_OCS = 0x0F, };