@@ -54,6 +54,11 @@ properties:
phy-names:
const: ufs-phy
+ sysreg:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for FSYS sysreg interface, used to control
+ sysreg register bit for UFS IO Coherency
+
required:
- compatible
- reg
@@ -12,6 +12,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/mfd/syscon.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
@@ -906,6 +907,10 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
goto out;
}
+ ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "sysreg");
+ if (IS_ERR(ufs->sysreg))
+ ufs->sysreg = NULL;
+
ufs->pclk_avail_min = PCLK_AVAIL_MIN;
ufs->pclk_avail_max = PCLK_AVAIL_MAX;
@@ -191,6 +191,7 @@ struct exynos_ufs {
struct ufs_phy_time_cfg t_cfg;
ktime_t entry_hibern8_t;
const struct exynos_ufs_drv_data *drv_data;
+ struct regmap *sysreg;
u32 opts;
#define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0)
UFS_EMBD sharability register of fsys block provides "sharability" setting of ufs-exynos. It can be set via syscon and regmap. Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- .../devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 5 +++++ drivers/scsi/ufs/ufs-exynos.c | 5 +++++ drivers/scsi/ufs/ufs-exynos.h | 1 + 3 files changed, 11 insertions(+)