| Message ID | 20220513061347.46480-5-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ufs: set power domain performance state when scaling gears | expand |
On 13-05-22, 08:13, Krzysztof Kozlowski wrote: > + ufs_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-50000000 { > + opp-hz = /bits/ 64 <50000000 > + 0 > + 0 > + 37500000 > + 0 > + 0 > + 0 > + 0 > + // FIXME: value 0 copied from freq-table-hz > + 0>; One general comment, I think this should follow how we specify multiple voltages or other fields and so each frequency should be part of a different < > braces. Like: opp-hz = /bits/ 64 <5000000>, <0>, .... Whatever is there between < > seems to be connected, like min/max/target for voltage. The code will process both in a similar way though eventually.
On 25/05/2022 09:16, Viresh Kumar wrote: > On 13-05-22, 08:13, Krzysztof Kozlowski wrote: >> + ufs_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-50000000 { >> + opp-hz = /bits/ 64 <50000000 >> + 0 >> + 0 >> + 37500000 >> + 0 >> + 0 >> + 0 >> + 0 >> + // FIXME: value 0 copied from freq-table-hz >> + 0>; > > One general comment, I think this should follow how we specify > multiple voltages or other fields and so each frequency should be part > of a different < > braces. Like: opp-hz = /bits/ 64 <5000000>, <0>, .... > > Whatever is there between < > seems to be connected, like > min/max/target for voltage. > > The code will process both in a similar way though eventually. OK, I can change to such format. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 692cf4be4eef..befcdd04d832 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1078,6 +1078,7 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SDM845_CX>; }; qfprom@784000 { @@ -2326,18 +2327,40 @@ ufs_mem_hc: ufshc@1d84000 { <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; + operating-points-v2 = <&ufs_opp_table>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000 + 0 + 0 + 37500000 + 0 + 0 + 0 + 0 + // FIXME: value 0 copied from freq-table-hz + 0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000 + 0 + 0 + 150000000 + 0 + 0 + 0 + 0 + 300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 {
UFS, when scaling gears, should choose appropriate performance state of RPMHPD power domain controller. Since UFS belongs to UFS_PHY_GDSC power domain, add necessary parent power domain to GCC. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 43 +++++++++++++++++++++------- 1 file changed, 33 insertions(+), 10 deletions(-)