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[122.107.196.14]) by smtp.gmail.com with ESMTPSA id y124-20020a62ce82000000b005258df7615bsm1571901pfg.0.2022.07.28.19.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jul 2022 19:05:29 -0700 (PDT) From: Daniil Lunev To: Adrian Hunter , Bart Van Assche , Greg Kroah-Hartman Cc: Daniil Lunev , Alim Akhtar , Andy Gross , Avri Altman , Bean Huo , Bjorn Andersson , Daejun Park , Eric Biggers , "James E.J. Bottomley" , Konrad Dybcio , "Martin K. Petersen" , Matthias Brugger , Mike Snitzer , Stanley Chu , Ulf Hansson , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-scsi@vger.kernel.org Subject: [PATCH v3 1/2] ufs: add function to check CRYPTO capability Date: Fri, 29 Jul 2022 12:05:07 +1000 Message-Id: <20220729120216.v3.1.I6b7934b96fff0d5ea22531e57c0a11f0ccd1acd8@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220729020508.4147751-1-dlunev@chromium.org> References: <20220729020508.4147751-1-dlunev@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org To align with other capability check functions. Signed-off-by: Daniil Lunev drivers/ufs/core/ufshcd-crypto.c | 8 ++++---- drivers/ufs/host/ufs-mediatek.c | 2 +- drivers/ufs/host/ufs-qcom-ice.c | 4 ++-- drivers/ufs/host/ufshcd-pci.c | 2 +- include/ufs/ufshcd.h | 5 +++++ 5 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/core/ufshcd-crypto.c b/drivers/ufs/core/ufshcd-crypto.c index 198360fe5e8e1..f819488bbde14 100644 --- a/drivers/ufs/core/ufshcd-crypto.c +++ b/drivers/ufs/core/ufshcd-crypto.c @@ -118,7 +118,7 @@ static int ufshcd_crypto_keyslot_evict(struct blk_crypto_profile *profile, bool ufshcd_crypto_enable(struct ufs_hba *hba) { - if (!(hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(hba)) return false; /* Reset might clear all keys, so reprogram all the keys. */ @@ -165,7 +165,7 @@ int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba) * hasn't advertised that crypto is supported. */ if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) || - !(hba->caps & UFSHCD_CAP_CRYPTO)) + !ufshcd_is_crypto_supported(hba)) goto out; hba->crypto_capabilities.reg_val = @@ -225,7 +225,7 @@ void ufshcd_init_crypto(struct ufs_hba *hba) { int slot; - if (!(hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(hba)) return; /* Clear all keyslots - the number of keyslots is (CFGC + 1) */ @@ -235,6 +235,6 @@ void ufshcd_init_crypto(struct ufs_hba *hba) void ufshcd_crypto_register(struct ufs_hba *hba, struct request_queue *q) { - if (hba->caps & UFSHCD_CAP_CRYPTO) + if (ufshcd_is_crypto_supported(hba)) blk_crypto_register(&hba->crypto_profile, q); } diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index beabc3ccd30b3..4bdf6a709126d 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -182,7 +182,7 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, ufs_mtk_host_reset(hba); } - if (hba->caps & UFSHCD_CAP_CRYPTO) + if (ufshcd_is_crypto_supported(hba)) ufs_mtk_crypto_enable(hba); if (host->caps & UFS_MTK_CAP_DISABLE_AH8) { diff --git a/drivers/ufs/host/ufs-qcom-ice.c b/drivers/ufs/host/ufs-qcom-ice.c index 745e48ec598f8..180a015b6973d 100644 --- a/drivers/ufs/host/ufs-qcom-ice.c +++ b/drivers/ufs/host/ufs-qcom-ice.c @@ -161,7 +161,7 @@ static void qcom_ice_optimization_enable(struct ufs_qcom_host *host) int ufs_qcom_ice_enable(struct ufs_qcom_host *host) { - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(host->hba)) return 0; qcom_ice_low_power_mode_enable(host); qcom_ice_optimization_enable(host); @@ -189,7 +189,7 @@ int ufs_qcom_ice_resume(struct ufs_qcom_host *host) { int err; - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(host->hba)) return 0; err = qcom_ice_wait_bist_status(host); diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c index 04166bda41daa..c06ccef348065 100644 --- a/drivers/ufs/host/ufshcd-pci.c +++ b/drivers/ufs/host/ufshcd-pci.c @@ -89,7 +89,7 @@ static int ufs_intel_hce_enable_notify(struct ufs_hba *hba, enum ufs_notify_change_status status) { /* Cannot enable ICE until after HC enable */ - if (status == POST_CHANGE && hba->caps & UFSHCD_CAP_CRYPTO) { + if (status == POST_CHANGE && ufshcd_is_crypto_supported(hba)) { u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); hce |= CRYPTO_GENERAL_ENABLE; diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index a92271421718e..ddbf470f8f455 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1005,6 +1005,11 @@ static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) return hba->caps & UFSHCD_CAP_WB_EN; } +static inline bool ufshcd_is_crypto_supported(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_CRYPTO; +} + #define ufshcd_writel(hba, val, reg) \ writel((val), (hba)->mmio_base + (reg)) #define ufshcd_readl(hba, reg) \