From patchwork Thu Sep 8 12:53:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sreekanth Reddy X-Patchwork-Id: 12970032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67479C54EE9 for ; Thu, 8 Sep 2022 12:41:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231899AbiIHMlf (ORCPT ); Thu, 8 Sep 2022 08:41:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231904AbiIHMlX (ORCPT ); Thu, 8 Sep 2022 08:41:23 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 177FDD076C for ; Thu, 8 Sep 2022 05:41:22 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id t3so12644641ply.2 for ; Thu, 08 Sep 2022 05:41:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date; bh=FQ98sBpGcvy+EEwifOpxCNgdcwc2Mdk46wztXTap1zE=; b=QbUy2ZNJ++y1IZFMQXZi8usvYIcFc00/DkL8XzuwZWSQTv/1aMHXRiEwqARArVzRyW H/bplcASLhoMnuRpl6cnbxUZ7sKsV9Y/SdHtDPKVwhUITfa0/PGGkJ9g9zCkavVc0HSV 6cyD5U9jxEx7CDVE5rOwxRp7OgkNCK9nlD55M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date; bh=FQ98sBpGcvy+EEwifOpxCNgdcwc2Mdk46wztXTap1zE=; b=m+AQgIOvsgbMJfu1IDMuY1zow0ukAZap6dZNtKUjhrQwcCpzIED5f/B4raCz2d4094 a6G9Ni57yo2m0afGDNSCsD/1+kT9eLFJ1HdMnHB6SSm2AM31I7cK7fqo4y2yf+RrsbJa ajEf1mn9D+eUJpX1B3W7hiJktkPF/Rra5qeecoGmYI4YqiDr0X9JYCBMV/QzVz0cx1Gw Txhj7NFOjr1niMbMJraiHj10/rRX80wYNtL3ki8wUypNgQmEjl0O6AXmV01h5/XAn9/k OuFkLGEL4SENkoxfkU7t/tpNFqwZiU11Y+1QAg4oHfpVYlAJgOazR7xdoL0ZArxJsQ9S Ow8g== X-Gm-Message-State: ACgBeo0qdErXyBvc+1NzRwZuwmgvrCpbVsNUmELw+ymuoLG/nBGssb4J mcE+xY/6sCEEAqvYs6/4Sx7fS/oNcvgg3MnCFXWsUVUQ7hs75SN61Bv7REqCpjvdz9lQrQkk9rt hBqAwsvq2qluLYAEDk2lq6pL45dzeZuPzrUdoT0JoVcpyrONdInFsc9Fpbn9vupGl5F555wFqoj l96FJQwiMh X-Google-Smtp-Source: AA6agR565BsHV/lscIKR/5q4B6UYzhiWZ1Uk4gNL7RbeQKvAFfH5s/qp9QzJnaejufwO5ZvsFVPSMw== X-Received: by 2002:a17:90b:38c1:b0:200:8f03:63d8 with SMTP id nn1-20020a17090b38c100b002008f0363d8mr4006489pjb.148.1662640881031; Thu, 08 Sep 2022 05:41:21 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id c17-20020a63ef51000000b0043395af24f6sm11106807pgk.25.2022.09.08.05.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 05:41:20 -0700 (PDT) From: Sreekanth Reddy To: linux-scsi@vger.kernel.org Cc: martin.petersen@oracle.com, Sreekanth Reddy Subject: [PATCH 3/9] mpi3mr: Schedule IRQ kthreads only on non-RT kernels Date: Thu, 8 Sep 2022 18:23:26 +0530 Message-Id: <20220908125332.21110-4-sreekanth.reddy@broadcom.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220908125332.21110-1-sreekanth.reddy@broadcom.com> References: <20220908125332.21110-1-sreekanth.reddy@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org In RT kernels, the IRQ handler's code is executed as a kernel thread. So, the driver is modified not to explicitly schedule the IRQ kernel thread. Signed-off-by: Sreekanth Reddy --- drivers/scsi/mpi3mr/mpi3mr_fw.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/mpi3mr/mpi3mr_fw.c b/drivers/scsi/mpi3mr/mpi3mr_fw.c index cc700e2..78792f2 100644 --- a/drivers/scsi/mpi3mr/mpi3mr_fw.c +++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c @@ -537,6 +537,7 @@ int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, if ((le16_to_cpu(reply_desc->reply_flags) & MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) break; +#ifndef CONFIG_PREEMPT_RT /* * Exit completion loop to avoid CPU lockup * Ensure remaining completion happens from threaded ISR. @@ -545,7 +546,7 @@ int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, op_reply_q->enable_irq_poll = true; break; } - +#endif } while (1); writel(reply_ci, @@ -614,6 +615,8 @@ static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) return IRQ_NONE; } +#ifndef CONFIG_PREEMPT_RT + static irqreturn_t mpi3mr_isr(int irq, void *privdata) { struct mpi3mr_intr_info *intr_info = privdata; @@ -691,6 +694,8 @@ static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) return IRQ_HANDLED; } +#endif + /** * mpi3mr_request_irq - Request IRQ and register ISR * @mrioc: Adapter instance reference @@ -713,8 +718,13 @@ static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", mrioc->driver_name, mrioc->id, index); +#ifndef CONFIG_PREEMPT_RT retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); +#else + retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary, + NULL, IRQF_SHARED, intr_info->name, intr_info); +#endif if (retval) { ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", intr_info->name, pci_irq_vector(pdev, index)); @@ -2179,9 +2189,13 @@ int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, pi = 0; op_req_q->pi = pi; +#ifndef CONFIG_PREEMPT_RT if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; +#else + atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios); +#endif writel(op_req_q->pi, &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);