diff mbox series

[v4,15/23] scsi: ufs: ufs-qcom: Use bitfields where appropriate

Message ID 20221201174328.870152-16-manivannan.sadhasivam@linaro.org (mailing list archive)
State Superseded
Headers show
Series ufs: qcom: Add HS-G4 support | expand

Commit Message

Manivannan Sadhasivam Dec. 1, 2022, 5:43 p.m. UTC 
Use bitfield macros where appropriate to simplify the driver.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++--------------------
 1 file changed, 28 insertions(+), 33 deletions(-)

Comments

Asutosh Das Dec. 5, 2022, 7:56 p.m. UTC | #1 
On Thu, Dec 01 2022 at 09:45 -0800, Manivannan Sadhasivam wrote:
>Use bitfield macros where appropriate to simplify the driver.
>
>Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>---
> drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++--------------------
> 1 file changed, 28 insertions(+), 33 deletions(-)
>
LGTM.

Reviewed-by: Asutosh Das <quic_asutoshd@quicinc.com>


>diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
>index 44466a395bb5..9d96ac71b27f 100644
>--- a/drivers/ufs/host/ufs-qcom.h
>+++ b/drivers/ufs/host/ufs-qcom.h
>@@ -17,12 +17,9 @@
> #define DEFAULT_CLK_RATE_HZ     1000000
> #define BUS_VECTOR_NAME_LEN     32
>
>-#define UFS_HW_VER_MAJOR_SHFT	(28)
>-#define UFS_HW_VER_MAJOR_MASK	(0x000F << UFS_HW_VER_MAJOR_SHFT)
>-#define UFS_HW_VER_MINOR_SHFT	(16)
>-#define UFS_HW_VER_MINOR_MASK	(0x0FFF << UFS_HW_VER_MINOR_SHFT)
>-#define UFS_HW_VER_STEP_SHFT	(0)
>-#define UFS_HW_VER_STEP_MASK	(0xFFFF << UFS_HW_VER_STEP_SHFT)
>+#define UFS_HW_VER_MAJOR_MASK	GENMASK(31, 28)
>+#define UFS_HW_VER_MINOR_MASK	GENMASK(27, 16)
>+#define UFS_HW_VER_STEP_MASK	GENMASK(15, 0)
>
> /* vendor specific pre-defined parameters */
> #define SLOW 1
>@@ -76,24 +73,28 @@ enum {
> #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)	(0x400 + x)
>
> /* bit definitions for REG_UFS_CFG1 register */
>-#define QUNIPRO_SEL		0x1
>-#define UTP_DBG_RAMS_EN		0x20000
>+#define QUNIPRO_SEL		BIT(0)
>+#define UFS_PHY_SOFT_RESET	BIT(1)
>+#define UTP_DBG_RAMS_EN		BIT(17)
> #define TEST_BUS_EN		BIT(18)
> #define TEST_BUS_SEL		GENMASK(22, 19)
> #define UFS_REG_TEST_BUS_EN	BIT(30)
>
>+#define UFS_PHY_RESET_ENABLE	1
>+#define UFS_PHY_RESET_DISABLE	0
>+
> /* bit definitions for REG_UFS_CFG2 register */
>-#define UAWM_HW_CGC_EN		(1 << 0)
>-#define UARM_HW_CGC_EN		(1 << 1)
>-#define TXUC_HW_CGC_EN		(1 << 2)
>-#define RXUC_HW_CGC_EN		(1 << 3)
>-#define DFC_HW_CGC_EN		(1 << 4)
>-#define TRLUT_HW_CGC_EN		(1 << 5)
>-#define TMRLUT_HW_CGC_EN	(1 << 6)
>-#define OCSC_HW_CGC_EN		(1 << 7)
>+#define UAWM_HW_CGC_EN		BIT(0)
>+#define UARM_HW_CGC_EN		BIT(1)
>+#define TXUC_HW_CGC_EN		BIT(2)
>+#define RXUC_HW_CGC_EN		BIT(3)
>+#define DFC_HW_CGC_EN		BIT(4)
>+#define TRLUT_HW_CGC_EN		BIT(5)
>+#define TMRLUT_HW_CGC_EN	BIT(6)
>+#define OCSC_HW_CGC_EN		BIT(7)
>
> /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
>-#define TEST_BUS_SUB_SEL_MASK	0x1F  /* All XXX_SEL fields are 5 bits wide */
>+#define TEST_BUS_SUB_SEL_MASK	GENMASK(4, 0)  /* All XXX_SEL fields are 5 bits wide */
>
> #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
> 				 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
>@@ -101,17 +102,11 @@ enum {
> 				 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
>
> /* bit offset */
>-enum {
>-	OFFSET_UFS_PHY_SOFT_RESET           = 1,
>-	OFFSET_CLK_NS_REG                   = 10,
>-};
>+#define OFFSET_CLK_NS_REG		0xa
>
> /* bit masks */
>-enum {
>-	MASK_UFS_PHY_SOFT_RESET             = 0x2,
>-	MASK_TX_SYMBOL_CLK_1US_REG          = 0x3FF,
>-	MASK_CLK_NS_REG                     = 0xFFFC00,
>-};
>+#define MASK_TX_SYMBOL_CLK_1US_REG	GENMASK(9, 0)
>+#define MASK_CLK_NS_REG			GENMASK(23, 10)
>
> /* QCOM UFS debug print bit mask */
> #define UFS_QCOM_DBG_PRINT_REGS_EN	BIT(0)
>@@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba,
> {
> 	u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
>
>-	*major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
>-	*minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
>-	*step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
>+	*major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
>+	*minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
>+	*step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
> };
>
> static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
> {
>-	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
>-			1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
>+	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE),
>+		    REG_UFS_CFG1);
>
> 	/*
> 	 * Make sure assertion of ufs phy reset is written to
>@@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
>
> static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
> {
>-	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
>-			0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
>+	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE),
>+		    REG_UFS_CFG1);
>
> 	/*
> 	 * Make sure de-assertion of ufs phy reset is written to
>-- 
>2.25.1
>
diff mbox series

Patch

diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 44466a395bb5..9d96ac71b27f 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -17,12 +17,9 @@ 
 #define DEFAULT_CLK_RATE_HZ     1000000
 #define BUS_VECTOR_NAME_LEN     32
 
-#define UFS_HW_VER_MAJOR_SHFT	(28)
-#define UFS_HW_VER_MAJOR_MASK	(0x000F << UFS_HW_VER_MAJOR_SHFT)
-#define UFS_HW_VER_MINOR_SHFT	(16)
-#define UFS_HW_VER_MINOR_MASK	(0x0FFF << UFS_HW_VER_MINOR_SHFT)
-#define UFS_HW_VER_STEP_SHFT	(0)
-#define UFS_HW_VER_STEP_MASK	(0xFFFF << UFS_HW_VER_STEP_SHFT)
+#define UFS_HW_VER_MAJOR_MASK	GENMASK(31, 28)
+#define UFS_HW_VER_MINOR_MASK	GENMASK(27, 16)
+#define UFS_HW_VER_STEP_MASK	GENMASK(15, 0)
 
 /* vendor specific pre-defined parameters */
 #define SLOW 1
@@ -76,24 +73,28 @@  enum {
 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)	(0x400 + x)
 
 /* bit definitions for REG_UFS_CFG1 register */
-#define QUNIPRO_SEL		0x1
-#define UTP_DBG_RAMS_EN		0x20000
+#define QUNIPRO_SEL		BIT(0)
+#define UFS_PHY_SOFT_RESET	BIT(1)
+#define UTP_DBG_RAMS_EN		BIT(17)
 #define TEST_BUS_EN		BIT(18)
 #define TEST_BUS_SEL		GENMASK(22, 19)
 #define UFS_REG_TEST_BUS_EN	BIT(30)
 
+#define UFS_PHY_RESET_ENABLE	1
+#define UFS_PHY_RESET_DISABLE	0
+
 /* bit definitions for REG_UFS_CFG2 register */
-#define UAWM_HW_CGC_EN		(1 << 0)
-#define UARM_HW_CGC_EN		(1 << 1)
-#define TXUC_HW_CGC_EN		(1 << 2)
-#define RXUC_HW_CGC_EN		(1 << 3)
-#define DFC_HW_CGC_EN		(1 << 4)
-#define TRLUT_HW_CGC_EN		(1 << 5)
-#define TMRLUT_HW_CGC_EN	(1 << 6)
-#define OCSC_HW_CGC_EN		(1 << 7)
+#define UAWM_HW_CGC_EN		BIT(0)
+#define UARM_HW_CGC_EN		BIT(1)
+#define TXUC_HW_CGC_EN		BIT(2)
+#define RXUC_HW_CGC_EN		BIT(3)
+#define DFC_HW_CGC_EN		BIT(4)
+#define TRLUT_HW_CGC_EN		BIT(5)
+#define TMRLUT_HW_CGC_EN	BIT(6)
+#define OCSC_HW_CGC_EN		BIT(7)
 
 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
-#define TEST_BUS_SUB_SEL_MASK	0x1F  /* All XXX_SEL fields are 5 bits wide */
+#define TEST_BUS_SUB_SEL_MASK	GENMASK(4, 0)  /* All XXX_SEL fields are 5 bits wide */
 
 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
 				 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
@@ -101,17 +102,11 @@  enum {
 				 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
 
 /* bit offset */
-enum {
-	OFFSET_UFS_PHY_SOFT_RESET           = 1,
-	OFFSET_CLK_NS_REG                   = 10,
-};
+#define OFFSET_CLK_NS_REG		0xa
 
 /* bit masks */
-enum {
-	MASK_UFS_PHY_SOFT_RESET             = 0x2,
-	MASK_TX_SYMBOL_CLK_1US_REG          = 0x3FF,
-	MASK_CLK_NS_REG                     = 0xFFFC00,
-};
+#define MASK_TX_SYMBOL_CLK_1US_REG	GENMASK(9, 0)
+#define MASK_CLK_NS_REG			GENMASK(23, 10)
 
 /* QCOM UFS debug print bit mask */
 #define UFS_QCOM_DBG_PRINT_REGS_EN	BIT(0)
@@ -135,15 +130,15 @@  ufs_qcom_get_controller_revision(struct ufs_hba *hba,
 {
 	u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
 
-	*major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
-	*minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
-	*step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
+	*major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
+	*minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
+	*step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
 };
 
 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
 {
-	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
-			1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
+	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE),
+		    REG_UFS_CFG1);
 
 	/*
 	 * Make sure assertion of ufs phy reset is written to
@@ -154,8 +149,8 @@  static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
 
 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
 {
-	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
-			0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
+	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE),
+		    REG_UFS_CFG1);
 
 	/*
 	 * Make sure de-assertion of ufs phy reset is written to