| Message ID | 20221201174328.870152-3-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ufs: qcom: Add HS-G4 support | expand |
On 1 December 2022 20:43:07 GMT+03:00, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: >Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead >of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's >rename all of the definitions to use "_ufsphy_". > >Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >--- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >index 20fcdbef8c77..35b77cd79e57 100644 >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >@@ -94,7 +94,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, > }; > >-static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = { >+static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), > QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), >@@ -143,12 +143,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), > }; > >-static const struct qmp_phy_init_tbl msm8996_ufs_tx[] = { >+static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { > QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), > QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), > }; > >-static const struct qmp_phy_init_tbl msm8996_ufs_rx[] = { >+static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { > QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), > QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), > QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), >@@ -629,15 +629,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { > .rx2 = 0xa00, > }; > >-static const struct qmp_phy_cfg msm8996_ufs_cfg = { >+static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { > .lanes = 1, > >- .serdes_tbl = msm8996_ufs_serdes, >- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes), >- .tx_tbl = msm8996_ufs_tx, >- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx), >- .rx_tbl = msm8996_ufs_rx, >- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx), >+ .serdes_tbl = msm8996_ufsphy_serdes, >+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes), >+ .tx_tbl = msm8996_ufsphy_tx, >+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx), >+ .rx_tbl = msm8996_ufsphy_rx, >+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx), > > .clk_list = msm8996_ufs_phy_clk_l, > .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), >@@ -1156,7 +1156,7 @@ static int qmp_ufs_probe(struct platform_device *pdev) > static const struct of_device_id qmp_ufs_of_match_table[] = { > { > .compatible = "qcom,msm8996-qmp-ufs-phy", >- .data = &msm8996_ufs_cfg, >+ .data = &msm8996_ufsphy_cfg, > }, { > .compatible = "qcom,msm8998-qmp-ufs-phy", > .data = &sdm845_ufsphy_cfg,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 20fcdbef8c77..35b77cd79e57 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -94,7 +94,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; -static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = { +static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -143,12 +143,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; -static const struct qmp_phy_init_tbl msm8996_ufs_tx[] = { +static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; -static const struct qmp_phy_init_tbl msm8996_ufs_rx[] = { +static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -629,15 +629,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { .rx2 = 0xa00, }; -static const struct qmp_phy_cfg msm8996_ufs_cfg = { +static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { .lanes = 1, - .serdes_tbl = msm8996_ufs_serdes, - .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes), - .tx_tbl = msm8996_ufs_tx, - .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx), - .rx_tbl = msm8996_ufs_rx, - .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx), + .serdes_tbl = msm8996_ufsphy_serdes, + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx_tbl = msm8996_ufsphy_tx, + .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx), + .rx_tbl = msm8996_ufsphy_rx, + .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx), .clk_list = msm8996_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -1156,7 +1156,7 @@ static int qmp_ufs_probe(struct platform_device *pdev) static const struct of_device_id qmp_ufs_of_match_table[] = { { .compatible = "qcom,msm8996-qmp-ufs-phy", - .data = &msm8996_ufs_cfg, + .data = &msm8996_ufsphy_cfg, }, { .compatible = "qcom,msm8998-qmp-ufs-phy", .data = &sdm845_ufsphy_cfg,
Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)