Message ID | 20230831130826.5592-2-peter.wang@mediatek.com (mailing list archive) |
---|---|
State | Accepted |
Headers | show |
Series | Fix abnormal clock scaling behaviors | expand |
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 129446775796..e3672e55efae 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1458,7 +1458,7 @@ static int ufshcd_devfreq_target(struct device *dev, ktime_to_us(ktime_sub(ktime_get(), start)), ret); out: - if (sched_clk_scaling_suspend_work) + if (sched_clk_scaling_suspend_work && !scale_up) queue_work(hba->clk_scaling.workq, &hba->clk_scaling.suspend_work);