| Message ID | 20231025085656.10848-2-chun-hung.wu@mediatek.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | ufs: core: Add host quirk QUIRK_MCQ_EXPAND_QUEUE_SLOT | expand |
On 10/25/23 01:56, Chun-Hung Wu wrote: > This quirk needs to be enabled if the host controller cannot > distinguish queue full or empty. From the UFSHCI 4.0 specification: "When the head and tail doorbells are equal, the queue is empty. [ ... ] When the head and tail doorbells are not equal, the queue contains queue entries." How is it possible that a host controller cannot distinguish queue full or queue empty? Which (head - tail) values cause trouble? More information is needed. Thanks, Bart.
On Wed, 2023-10-25 at 11:10 -0700, Bart Van Assche wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On 10/25/23 01:56, Chun-Hung Wu wrote: > > This quirk needs to be enabled if the host controller cannot > > distinguish queue full or empty. > > From the UFSHCI 4.0 specification: "When the head and tail doorbells > are > equal, the queue is empty. [ ... ] When the head and tail doorbells > are > not equal, the queue contains queue entries." > > How is it possible that a host controller cannot distinguish queue > full > or queue empty? Which (head - tail) values cause trouble? More > information is needed. > > Thanks, > > Bart. > From UFSHCI 4.0 spec "When the head and tail doorbells are equal, the queue is empty. *Nothe that this definition means there will always be one empty queue entry" One of our platform does not keep one empty queue entry for CQ full case, that's why we need this patch to fix this corner case. Thanks, Chun-Hung
On 10/26/23 20:27, Chun-Hung Wu (巫駿宏) wrote: > From UFSHCI 4.0 spec "When the head and tail doorbells are equal, the > queue is empty. *Nothe that this definition means there will always be > one empty queue entry" > One of our platform does not keep one empty queue > entry for CQ full > case, that's why we need this patch to fix this corner case. The UFSHCI driver should make sure that there is always one empty queue entry. Does "platform" in the above text refer to the SoC that includes the UFSHCI controller? What is totally unclear to me is why the following code depends on the UFSHCI controller type: + if (ufshcd_is_mcq_expand_queue_slot(hba)) + hwq->max_entries = hba->nutrs + 1; + else + hwq->max_entries = hba->nutrs; Shouldn't hwq->max_entries = hba->nutrs + 1 be used for all UFSHCI 4.0 controllers? Thanks, Bart.
On Fri, 2023-10-27 at 13:55 -0700, Bart Van Assche wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On 10/26/23 20:27, Chun-Hung Wu (巫駿宏) wrote: > > From UFSHCI 4.0 spec "When the head and tail doorbells are equal, > the > > queue is empty. *Nothe that this definition means there will always > be > > one empty queue entry" > > One of our platform does not keep one empty queue > > entry for CQ full > > case, that's why we need this patch to fix this corner case. > > The UFSHCI driver should make sure that there is always one empty > queue > entry. Does "platform" in the above text refer to the SoC that > includes > the UFSHCI controller? Yes here "platform" indicates SoC that includes the UFSHCI controller. > > What is totally unclear to me is why the following code depends on > the > UFSHCI controller type: > > +if (ufshcd_is_mcq_expand_queue_slot(hba)) > +hwq->max_entries = hba->nutrs + 1; > +else > +hwq->max_entries = hba->nutrs; > > Shouldn't hwq->max_entries = hba->nutrs + 1 be used for all UFSHCI > 4.0 > controllers? > > Thanks, > > Bart. > I think UFSHCI 4.0 spec "When the head and tail doorbells are equal,the queue is empty. *Nothe that this definition means there will alwaysbe one empty queue entry" means that "UFSHCI controller" should always keep one empty queue entry. One of our host does not follow the spec, therefore, this host will treat CQ full(head = tail) as CQ empty (head = tail). That's why we propose this quirk to expand one queue slot for hosts have such issue. It will make CQ full(head != tail)[keep one empty queue entry] not equal to CQ empty(head = tail). hwq->max_entries will be used to set SQ&CQ size in SQ&CQ Configuration Registers, we think it should only apply to specific hosts need this quirk not all. Thanks, Chun-Hung
diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 2ba8ec254dce..9b8ed3f9a349 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -436,7 +436,10 @@ int ufshcd_mcq_init(struct ufs_hba *hba) for (i = 0; i < hba->nr_hw_queues; i++) { hwq = &hba->uhq[i]; - hwq->max_entries = hba->nutrs; + if (ufshcd_is_mcq_expand_queue_slot(hba)) + hwq->max_entries = hba->nutrs + 1; + else + hwq->max_entries = hba->nutrs; spin_lock_init(&hwq->sq_lock); spin_lock_init(&hwq->cq_lock); mutex_init(&hwq->sq_mutex); diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 7d07b256e906..44de185501b5 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -643,6 +643,12 @@ enum ufshcd_quirks { * thus need this quirk to skip related flow. */ UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, + + /* + * This quirk needs to be enabled if the host controller cannot + * distinguish queue full or empty. + */ + UFSHCD_QUIRK_MCQ_EXPAND_QUEUE_SLOT = 1 << 22, }; enum ufshcd_caps { @@ -1198,6 +1204,11 @@ static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; } +static inline bool ufshcd_is_mcq_expand_queue_slot(struct ufs_hba *hba) +{ + return hba->quirks & UFSHCD_QUIRK_MCQ_EXPAND_QUEUE_SLOT; +} + #define ufsmcq_writel(hba, val, reg) \ writel((val), (hba)->mcq_base + (reg)) #define ufsmcq_readl(hba, reg) \