| Message ID | 20240531103821.1583934-2-minwoo.im@samsung.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ufs: pci: Add support UFSHCI 4.0 MCQ | expand |
On 5/31/24 03:38, Minwoo Im wrote: > This helper returns an offset address of MCQ queue configuration > registers. This is a prep patch for the following patch. > > Signed-off-by: Minwoo Im <minwoo.im@samsung.com> > --- > drivers/ufs/core/ufs-mcq.c | 14 ++++++++++++++ > include/ufs/ufshcd.h | 1 + > 2 files changed, 15 insertions(+) > > diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c > index 52210c4c20dc..46faa54aea94 100644 > --- a/drivers/ufs/core/ufs-mcq.c > +++ b/drivers/ufs/core/ufs-mcq.c > @@ -18,6 +18,7 @@ > #include <linux/iopoll.h> > > #define MAX_QUEUE_SUP GENMASK(7, 0) > +#define QCFGPTR GENMASK(23, 16) > #define UFS_MCQ_MIN_RW_QUEUES 2 > #define UFS_MCQ_MIN_READ_QUEUES 0 > #define UFS_MCQ_MIN_POLL_QUEUES 0 > @@ -116,6 +117,19 @@ struct ufs_hw_queue *ufshcd_mcq_req_to_hwq(struct ufs_hba *hba, > return &hba->uhq[hwq]; > } > > +/** > + * ufshcd_mcq_queue_cfg_addr - get an start address of the MCQ Queue Config > + * Registers. > + * @hba: per adapter instance > + * > + * Return: Start address of MCQ Queue Config Registers in HCI > + */ > +unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba) > +{ > + return FIELD_GET(QCFGPTR, hba->mcq_capabilities) * 0x200; > +} > +EXPORT_SYMBOL_GPL(ufshcd_mcq_queue_cfg_addr); > + > /** > * ufshcd_mcq_decide_queue_depth - decide the queue depth > * @hba: per adapter instance > diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h > index df68fb1d4f3f..9e0581115b34 100644 > --- a/include/ufs/ufshcd.h > +++ b/include/ufs/ufshcd.h > @@ -1278,6 +1278,7 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); > void ufshcd_hba_stop(struct ufs_hba *hba); > void ufshcd_schedule_eh_work(struct ufs_hba *hba); > void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); > +unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba); > u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); > void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); > unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, New functions should not be introduced as a separate patch but instead should be introduced in the first patch that adds a caller to the new function. Thanks, Bart.
On 24-05-31 13:15:11, Bart Van Assche wrote: > On 5/31/24 03:38, Minwoo Im wrote: > > This helper returns an offset address of MCQ queue configuration > > registers. This is a prep patch for the following patch. > > > > Signed-off-by: Minwoo Im <minwoo.im@samsung.com> > > --- > > drivers/ufs/core/ufs-mcq.c | 14 ++++++++++++++ > > include/ufs/ufshcd.h | 1 + > > 2 files changed, 15 insertions(+) > > > > diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c > > index 52210c4c20dc..46faa54aea94 100644 > > --- a/drivers/ufs/core/ufs-mcq.c > > +++ b/drivers/ufs/core/ufs-mcq.c > > @@ -18,6 +18,7 @@ > > #include <linux/iopoll.h> > > #define MAX_QUEUE_SUP GENMASK(7, 0) > > +#define QCFGPTR GENMASK(23, 16) > > #define UFS_MCQ_MIN_RW_QUEUES 2 > > #define UFS_MCQ_MIN_READ_QUEUES 0 > > #define UFS_MCQ_MIN_POLL_QUEUES 0 > > @@ -116,6 +117,19 @@ struct ufs_hw_queue *ufshcd_mcq_req_to_hwq(struct ufs_hba *hba, > > return &hba->uhq[hwq]; > > } > > +/** > > + * ufshcd_mcq_queue_cfg_addr - get an start address of the MCQ Queue Config > > + * Registers. > > + * @hba: per adapter instance > > + * > > + * Return: Start address of MCQ Queue Config Registers in HCI > > + */ > > +unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba) > > +{ > > + return FIELD_GET(QCFGPTR, hba->mcq_capabilities) * 0x200; > > +} > > +EXPORT_SYMBOL_GPL(ufshcd_mcq_queue_cfg_addr); > > + > > /** > > * ufshcd_mcq_decide_queue_depth - decide the queue depth > > * @hba: per adapter instance > > diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h > > index df68fb1d4f3f..9e0581115b34 100644 > > --- a/include/ufs/ufshcd.h > > +++ b/include/ufs/ufshcd.h > > @@ -1278,6 +1278,7 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); > > void ufshcd_hba_stop(struct ufs_hba *hba); > > void ufshcd_schedule_eh_work(struct ufs_hba *hba); > > void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); > > +unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba); > > u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); > > void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); > > unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, > > New functions should not be introduced as a separate patch but instead should > be introduced in the first patch that adds a caller to the new function. I will squash it to the second one and udpate it in the next version. > > Thanks, > > Bart. >
diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 52210c4c20dc..46faa54aea94 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -18,6 +18,7 @@ #include <linux/iopoll.h> #define MAX_QUEUE_SUP GENMASK(7, 0) +#define QCFGPTR GENMASK(23, 16) #define UFS_MCQ_MIN_RW_QUEUES 2 #define UFS_MCQ_MIN_READ_QUEUES 0 #define UFS_MCQ_MIN_POLL_QUEUES 0 @@ -116,6 +117,19 @@ struct ufs_hw_queue *ufshcd_mcq_req_to_hwq(struct ufs_hba *hba, return &hba->uhq[hwq]; } +/** + * ufshcd_mcq_queue_cfg_addr - get an start address of the MCQ Queue Config + * Registers. + * @hba: per adapter instance + * + * Return: Start address of MCQ Queue Config Registers in HCI + */ +unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba) +{ + return FIELD_GET(QCFGPTR, hba->mcq_capabilities) * 0x200; +} +EXPORT_SYMBOL_GPL(ufshcd_mcq_queue_cfg_addr); + /** * ufshcd_mcq_decide_queue_depth - decide the queue depth * @hba: per adapter instance diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index df68fb1d4f3f..9e0581115b34 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1278,6 +1278,7 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); void ufshcd_hba_stop(struct ufs_hba *hba); void ufshcd_schedule_eh_work(struct ufs_hba *hba); void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); +unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba); u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
This helper returns an offset address of MCQ queue configuration registers. This is a prep patch for the following patch. Signed-off-by: Minwoo Im <minwoo.im@samsung.com> --- drivers/ufs/core/ufs-mcq.c | 14 ++++++++++++++ include/ufs/ufshcd.h | 1 + 2 files changed, 15 insertions(+)