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[60.248.88.209]) by smtp.gmail.com with ESMTPSA id s11sm1844594pgm.36.2020.10.07.00.26.51 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Oct 2020 00:26:52 -0700 (PDT) Message-ID: <7dc957d8e16d04cb9605bef10e474acc52235190.camel@areca.com.tw> Subject: [PATCH v3 1/2] scsi: arcmsr: Use upper_32_bits() instead of dma_addr_hi32() From: ching Huang To: martin.petersen@oracle.com, James.Bottomley@HansenPartnership.com, linux-scsi@vger.kernel.org, Linux Kernel Mailing List Date: Wed, 07 Oct 2020 15:26:52 +0800 X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) Mime-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: ching Huang Use upper_32_bits() instead of dma_addr_hi32(). Signed-off-by: ching Huang diff --git a/drivers/scsi/arcmsr/arcmsr_hba.c b/drivers/scsi/arcmsr/arcmsr_hba.c index d13d672..55d85c9 100644 --- a/drivers/scsi/arcmsr/arcmsr_hba.c +++ b/drivers/scsi/arcmsr/arcmsr_hba.c @@ -653,9 +653,9 @@ static void arcmsr_hbaF_assign_regAddr(struct AdapterControlBlock *acb) 3) >> 2) << 2; pmuF = acb->pmuF; /* host buffer low address, bit0:1 all buffer active */ - writel((uint32_t)(host_buffer_dma | 1), &pmuF->inbound_msgaddr0); + writel(lower_32_bits(host_buffer_dma | 1), &pmuF->inbound_msgaddr0); /* host buffer high address */ - writel(dma_addr_hi32(host_buffer_dma), &pmuF->inbound_msgaddr1); + writel(upper_32_bits(host_buffer_dma), &pmuF->inbound_msgaddr1); /* set host buffer physical address */ writel(ARCMSR_HBFMU_DOORBELL_SYNC1, &pmuF->iobound_doorbell); } @@ -4057,11 +4057,8 @@ static int arcmsr_iop_confirm(struct AdapterControlBlock *acb) writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]); writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]); writel(acb->ccbsize, ®->msgcode_rwbuffer[4]); - dma_coherent_handle = acb->dma_coherent_handle2; - cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff); - cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16); - writel(cdb_phyaddr, ®->msgcode_rwbuffer[5]); - writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[6]); + writel(lower_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[5]); + writel(upper_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[6]); writel(acb->ioqueue_size, ®->msgcode_rwbuffer[7]); writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; @@ -4081,11 +4078,8 @@ static int arcmsr_iop_confirm(struct AdapterControlBlock *acb) acb->msgcode_rwbuffer[2] = cdb_phyaddr; acb->msgcode_rwbuffer[3] = cdb_phyaddr_hi32; acb->msgcode_rwbuffer[4] = acb->ccbsize; - dma_coherent_handle = acb->dma_coherent_handle2; - cdb_phyaddr = (uint32_t)dma_coherent_handle; - cdb_phyaddr_hi32 = dma_addr_hi32(dma_coherent_handle); - acb->msgcode_rwbuffer[5] = cdb_phyaddr; - acb->msgcode_rwbuffer[6] = cdb_phyaddr_hi32; + acb->msgcode_rwbuffer[5] = lower_32_bits(acb->dma_coherent_handle2); + acb->msgcode_rwbuffer[6] = upper_32_bits(acb->dma_coherent_handle2); acb->msgcode_rwbuffer[7] = acb->completeQ_size; writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;