From patchwork Thu Jun 15 12:17:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 9788773 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0C93360325 for ; Thu, 15 Jun 2017 12:24:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE8B6284BB for ; Thu, 15 Jun 2017 12:24:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E35B4285EA; Thu, 15 Jun 2017 12:24:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8BDB0284BB for ; Thu, 15 Jun 2017 12:24:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752358AbdFOMXm (ORCPT ); Thu, 15 Jun 2017 08:23:42 -0400 Received: from kvm5.telegraphics.com.au ([98.124.60.144]:49210 "EHLO kvm5.telegraphics.com.au" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751623AbdFOMXl (ORCPT ); Thu, 15 Jun 2017 08:23:41 -0400 X-Greylist: delayed 344 seconds by postgrey-1.27 at vger.kernel.org; Thu, 15 Jun 2017 08:23:41 EDT Received: by kvm5.telegraphics.com.au (Postfix, from userid 502) id 94D0329C5A; Thu, 15 Jun 2017 08:17:56 -0400 (EDT) To: "James E.J. Bottomley" , "Martin K. Petersen" , Ondrej Zary Cc: , , Michael Schmitz Message-Id: In-Reply-To: References: From: Finn Thain Subject: [PATCH 2/4] g_NCR5380: End PDMA transfer correctly on target disconnection Date: Thu, 15 Jun 2017 08:17:56 -0400 (EDT) Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ondrej Zary When an IRQ arrives during PDMA transfer, pread() and pwrite() return without waiting for the 53C80 registers to be ready and this ends up messing up the chip state. This was observed with SONY CDU-55S which is slow enough to disconnect during 4096-byte reads. IRQ during PDMA is not an error so don't return -1. Instead, store the remaining byte count for use by NCR5380_dma_residual(). [Modified to improve the BASR_END_DMA_TRANSFER error message rather than remove it -- F.T.] Signed-off-by: Ondrej Zary Signed-off-by: Finn Thain --- drivers/scsi/g_NCR5380.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/scsi/g_NCR5380.c b/drivers/scsi/g_NCR5380.c index 14ef4e8c4713..1e1cf7ca86fa 100644 --- a/drivers/scsi/g_NCR5380.c +++ b/drivers/scsi/g_NCR5380.c @@ -44,12 +44,13 @@ int c400_ctl_status; \ int c400_blk_cnt; \ int c400_host_buf; \ - int io_width + int io_width; \ + int pdma_residual #define NCR5380_dma_xfer_len generic_NCR5380_dma_xfer_len #define NCR5380_dma_recv_setup generic_NCR5380_pread #define NCR5380_dma_send_setup generic_NCR5380_pwrite -#define NCR5380_dma_residual NCR5380_dma_residual_none +#define NCR5380_dma_residual generic_NCR5380_dma_residual #define NCR5380_intr generic_NCR5380_intr #define NCR5380_queue_command generic_NCR5380_queue_command @@ -500,10 +501,8 @@ static inline int generic_NCR5380_pread(struct NCR5380_hostdata *hostdata, while (1) { if (NCR5380_read(hostdata->c400_blk_cnt) == 0) break; - if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) { - printk(KERN_ERR "53C400r: Got 53C80_IRQ start=%d, blocks=%d\n", start, blocks); - return -1; - } + if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) + goto out_wait; while (NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) ; /* FIXME - no timeout */ @@ -542,13 +541,16 @@ static inline int generic_NCR5380_pread(struct NCR5380_hostdata *hostdata, if (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ)) printk("53C400r: no 53C80 gated irq after transfer"); +out_wait: /* wait for 53C80 registers to be available */ while (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)) ; if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) - printk(KERN_ERR "53C400r: no end dma signal\n"); - + pr_err("%s: No end dma signal (%d/%d)\n", __func__, start, len); + + hostdata->pdma_residual = len - start; + return 0; } @@ -571,10 +573,8 @@ static inline int generic_NCR5380_pwrite(struct NCR5380_hostdata *hostdata, NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); NCR5380_write(hostdata->c400_blk_cnt, blocks); while (1) { - if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) { - printk(KERN_ERR "53C400w: Got 53C80_IRQ start=%d, blocks=%d\n", start, blocks); - return -1; - } + if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) + goto out_wait; if (NCR5380_read(hostdata->c400_blk_cnt) == 0) break; @@ -612,15 +612,17 @@ static inline int generic_NCR5380_pwrite(struct NCR5380_hostdata *hostdata, blocks--; } +out_wait: /* wait for 53C80 registers to be available */ while (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)) { udelay(4); /* DTC436 chip hangs without this */ /* FIXME - no timeout */ } - if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) { - printk(KERN_ERR "53C400w: no end dma signal\n"); - } + if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) + pr_err("%s: No end dma signal (%d/%d)\n", __func__, start, len); + + hostdata->pdma_residual = len - start; while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) ; // TIMEOUT @@ -642,6 +644,11 @@ static int generic_NCR5380_dma_xfer_len(struct NCR5380_hostdata *hostdata, return min(transfersize, DMA_MAX_SIZE); } +static int generic_NCR5380_dma_residual(struct NCR5380_hostdata *hostdata) +{ + return hostdata->pdma_residual; +} + /* * Include the NCR5380 core code that we build our driver around */