From patchwork Fri Jan 10 13:19:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11327375 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF7766C1 for ; Fri, 10 Jan 2020 13:19:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BE79E2072E for ; Fri, 10 Jan 2020 13:19:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727595AbgAJNTk (ORCPT ); Fri, 10 Jan 2020 08:19:40 -0500 Received: from laurent.telenet-ops.be ([195.130.137.89]:51718 "EHLO laurent.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727641AbgAJNTb (ORCPT ); Fri, 10 Jan 2020 08:19:31 -0500 Received: from ramsan ([84.195.182.253]) by laurent.telenet-ops.be with bizsmtp id odKU210085USYZQ01dKUuP; Fri, 10 Jan 2020 14:19:28 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1ipuCG-0007Wm-93; Fri, 10 Jan 2020 14:19:28 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1ipuCG-0000Hi-7A; Fri, 10 Jan 2020 14:19:28 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 00/13] pinctrl: sh-pfc: checker: Various improvements Date: Fri, 10 Jan 2020 14:19:14 +0100 Message-Id: <20200110131927.1029-1-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Hi all, This patch series contains various improvements for the builtin pin control table runtime checks of the Renesas Pin Function Controller driver. These checks are enabled with CONFIG_DEBUG_PINCTRL=y, which can be combined with CONFIG_COMPILE_TEST=y to increase coverage to all Renesas ARM and SuperH SoCs.. Note that all issues detected by this have already been fixed in "[PATCH 0/6] pinctrl: sh-pfc: More miscellenaous fixes"[1], and are now part of linux-next. I plan to queue this in sh-pfc-for-v5.7. Thanks for your comments! [1] https://lore.kernel.org/linux-renesas-soc/20191218194812.12741-1-geert+renesas@glider.be/ Geert Uytterhoeven (13): pinctrl: sh-pfc: checker: Move data before code pinctrl: sh-pfc: checker: Add helpers for reporting pinctrl: sh-pfc: checker: Add helper for safe name comparison pinctrl: sh-pfc: checker: Add check for config register conflicts pinctrl: sh-pfc: checker: Add check for enum ID conflicts pinctrl: sh-pfc: checker: Improve pin checks pinctrl: sh-pfc: checker: Improve pin function checks pinctrl: sh-pfc: checker: Improve pin group checks pinctrl: sh-pfc: checker: Add drive strength register checks pinctrl: sh-pfc: checker: Add bias register checks pinctrl: sh-pfc: checker: Add ioctrl register checks pinctrl: sh-pfc: checker: Add data register checks pinctrl: sh-pfc: checker: Add function GPIO checks drivers/pinctrl/sh-pfc/core.c | 312 +++++++++++++++++++++++++++------- 1 file changed, 250 insertions(+), 62 deletions(-) Reviewed-by: Niklas Söderlund