deleted file mode 100644
@@ -1,51 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/cpu.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/irqflags.h>
-#include <linux/irq.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/cacheflush.h>
-
-#undef dbg_print
-
-#ifdef CONFIG_PM_DEBUG
-#define dbg_print(fmt, args...) \
- printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
-#else
-#define dbg_print(fmt, args...)
-#endif
-
-/*
- * saved registers:
- * - 8 gpr
- * - pr
- * - sr
- * - r6_bank
- * - r7_bank
- */
-unsigned long saved_context_reg[12] __cacheline_aligned;
-
-/* References to section boundaries */
-int pfn_is_nosave(unsigned long pfn)
-{
- unsigned long nosave_begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT;
- unsigned long nosave_end_pfn =
- PAGE_ALIGN(__pa(&__nosave_end)) >> PAGE_SHIFT;
- return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
-
-}
deleted file mode 100644
@@ -1,88 +0,0 @@
-/*
- * platform Pm capability - STb710x
- *
- * Copyright (C) 2009 STMicroelectronics Limited
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/stm/pm.h>
-
-#ifdef CONFIG_PM
-static int
-usb_pm_pwd_dwn(struct platform_device *dev, int host_phy, int pwd)
-{
- static struct sysconf_field *sc;
-
- if(!sc)
- sc = sysconf_claim(SYS_CFG, 2, 4, 5, "usb rx/tx");
-
- sysconf_write(sc, (pwd ? 0 : 3));
- return 0;
-}
-
-static int
-usb_pm_pwd_ack(struct platform_device *dev, int host_phy, int ack)
-{
- /* It isn't clear what the SysSTA_0 does... */
- mdelay(10);
- return 0;
-}
-
-static int
-usb_pm_sw_reset(struct platform_device *dev)
-{
- static struct sysconf_field *sc;
- unsigned long reg;
-
- if (!sc)
- sc = sysconf_claim(SYS_CFG, 2, 1, 1, "usb reset");
- reg = sysconf_read(sc);
- if (reg) {
- sysconf_write(sc, 0);
- mdelay(30);
- }
- return 0;
-}
-
-/*
- * The EMI sysconf capabilities seems not working!
- */
-static int
-emi_pwd_dwn_req(struct platform_device *pdev, int host_phy, int down)
-{
- static struct sysconf_field *sc;
- if (!sc)
- sc = sysconf_claim(SYS_CFG, 32, 1, 1, "emi pwr req");
-
-/* sysconf_write(sc, (down ? 1 : 0));*/
-
- return 0;
-}
-
-static int
-emi_pwd_dwn_ack(struct platform_device *pdev, int host_phy, int ack)
-{
- static struct sysconf_field *sc;
- int i;
-
- if (!sc)
- sc = sysconf_claim(SYS_STA, 15, 0, 0, "emi pwr ack");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static struct platform_device_pm stx7100_pm_devices[] = {
-pm_plat_dev(&st_usb_device, NULL, usb_pm_pwd_dwn, usb_pm_pwd_ack,
- usb_pm_sw_reset),
-pm_plat_dev(&emi, NULL, emi_pwd_dwn_req, emi_pwd_dwn_ack, NULL),
-};
-
-#endif
deleted file mode 100644
@@ -1,75 +0,0 @@
-/*
- * Platform PM Capability - STx5197
- *
- * Copyright (C) 2008 STMicroelectronics Limited
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/stm/pm.h>
-#include <linux/delay.h>
-#ifdef CONFIG_PM
-static int
-usb_pwr_ack(struct platform_device *dev, int host_phy, int on)
-{
- static struct sysconf_field *sc;
- int i;
- if (!sc)
- sc = sysconf_claim(CFG_MONITOR_E, 30, 30, "USB");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == on)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static int
-usb_pwr_dwn(struct platform_device *dev, int host_phy, int pwd)
-{
- static struct sysconf_field *sc;
-
- /* Power on USB */
- if (!sc) {
- sc = sysconf_claim(CFG_CTRL_H, 8, 8, "USB");
- }
-
- sysconf_write(sc, (pwd ? 1 : 0));
-
- return 0;
-}
-
-static int
-emi_pwr_dwn_req(struct platform_device *dev, int host_phy, int dwn)
-{
- static struct sysconf_field *sc;
- if (!sc)
- sc = sysconf_claim(CFG_CTRL_I, 31, 31, "emi pwd req");
-
- sysconf_write(sc, (dwn ? 1 : 0));
- return 0;
-}
-
-static int
-emi_pwr_dwn_ack(struct platform_device *dev, int host_phy, int ack)
-{
- static struct sysconf_field *sc;
- int i;
- if (!sc)
- sc = sysconf_claim(CFG_MONITOR_J, 20, 20, "emi pwr ack");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-
-static struct platform_device_pm stx5197_pm_devices[] = {
-pm_plat_dev(&emi, NULL, emi_pwr_dwn_req, emi_pwr_dwn_ack, NULL),
-pm_plat_dev(&st_usb, NULL, usb_pwr_dwn, usb_pwr_ack, NULL),
-};
-#endif
deleted file mode 100644
@@ -1,83 +0,0 @@
-/*
- * Platform PM Capability STx7105
- *
- * Copyright (C) 2009 STMicroelectronics Limited
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/stm/pm.h>
-#ifdef CONFIG_PM
-static int
-emi_pwr_dwn_req(struct platform_device *dev, int host_phy, int dwn)
-{
- static struct sysconf_field *sc;
- if (!sc)
- sc = sysconf_claim(SYS_CFG, 12, 1, 1, "emi pwr req");
-
- sysconf_write(sc, (dwn ? 1 : 0));
- return 0;
-}
-
-static int
-emi_pwr_dwn_ack(struct platform_device *dev, int host_phy, int ack)
-{
- static struct sysconf_field *sc;
- int i;
- if (!sc)
- sc = sysconf_claim(SYS_STA, 15, 1, 1, "emi pwr ack");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static int
-usb_pwr_req(struct platform_device *dev, int host_phy, int dwn)
-{
- static struct sysconf_field *sc[2];
- static struct sysconf_field *sc_phy[2];
- int port = dev->id;
- if (!sc[port]) {
- sc_phy[port] = sysconf_claim(SYS_CFG, 32, 6+port, 6+port,
- "USB phy");
- sc[port] = sysconf_claim(SYS_CFG, 32, 4+port, 4+port, "USB");
- }
-
- sysconf_write(sc[port], (dwn ? 1 : 0));
- sysconf_write(sc_phy[port], (dwn ? 1 : 0));
- return 0;
-}
-
-static int
-usb_pwr_ack(struct platform_device *dev, int host_phy, int ack)
-{
- static struct sysconf_field *sc[2];
- int port = dev->id;
- int i;
- if (!sc[port])
- sc[port] = sysconf_claim(SYS_STA, 15, 4 + port, 4 + port, "USB");
-
- for (i = 5; i; --i) {
- if (sysconf_read(sc[port]) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static struct platform_device_pm stx7105_pm_devices[] = {
-pm_plat_dev(&emi, NULL, emi_pwr_dwn_req, emi_pwr_dwn_ack, NULL),
-pm_plat_dev(&usb_device[0], NULL, usb_pwr_req, usb_pwr_ack, NULL),
-pm_plat_dev(&usb_device[1], NULL, usb_pwr_req, usb_pwr_ack, NULL),
-/*
- * There should be also the SATA entry... but:
- * - on cut 1 they are broken ...
- * - on cut 2 there should be only one ...
- */
-};
-#endif
deleted file mode 100644
@@ -1,94 +0,0 @@
-/*
- * Platform PM Capability - STx7111
- *
- * Copyright (C) 2009 STMicroelectronics Limited
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/stm/pm.h>
-#ifdef CONFIG_PM
-static int
-usb_pwr_ack(struct platform_device *dev, int host_phy, int on)
-{
- static struct sysconf_field *sc;
- int i;
-
- if (!sc)
- sc = sysconf_claim(SYS_STA, 15, 4, 4, "USB_PW_ACK");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == on)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static int
-usb_pwr_dwn(struct platform_device *dev, int host_phy, int pwd)
-{
- static struct sysconf_field *sc, *sc_clk;
-
- /* Power on USB */
- if (!sc) {
- sc = sysconf_claim(SYS_CFG, 32, 4, 4, "USB_PW_REQ");
- sc_clk = sysconf_claim(SYS_CFG, 40, 2, 3, "usb_clk");
- }
-
- sysconf_write(sc, (pwd ? 1 : 0));
- sysconf_write(sc_clk, (pwd ? 3 : 0));
-
- return 0;
-}
-
-static int
-usb_sw_reset(struct platform_device *dev, int host_phy)
-{
- static struct sysconf_field *sc;
-
- /* Reset USB */
- if (!sc)
- sc = sysconf_claim(SYS_CFG, 4, 4, 4, "USB_RST");
- sysconf_write(sc, 0);
- mdelay(10);
- sysconf_write(sc, 1);
- mdelay(10);
-
- return 0;
-}
-
-
-static int
-emi_pwr_dwn_req(struct platform_device *dev, int host_phy, int dwn)
-{
- static struct sysconf_field *sc;
- if (!sc)
- sc = sysconf_claim(SYS_CFG, 32, 1, 1, "emi pwr");
-
- sysconf_write(sc, (dwn ? 1 : 0));
- return 0;
-}
-
-static int
-emi_pwr_dwn_ack(struct platform_device *dev, int host_phy, int ack)
-{
- static struct sysconf_field *sc;
- int i;
- if (!sc)
- sc = sysconf_claim(SYS_STA, 15, 1, 1, "emi pwr ack");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-
-static struct platform_device_pm stx7111_pm_devices[] = {
-pm_plat_dev(&emi, NULL, emi_pwr_dwn_req, emi_pwr_dwn_ack, NULL),
-pm_plat_dev(&st_usb, NULL, usb_pwr_dwn, usb_pwr_ack, usb_sw_reset),
-};
-#endif
deleted file mode 100644
@@ -1,76 +0,0 @@
-/*
- * Platform PM Capability - STx7141
- *
- * Copyright (C) 2009 STMicroelectronics Limited
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/stm/pm.h>
-
-#ifdef CONFIG_PM
-static int
-usb_pwr_req(struct platform_device *dev, int host_phy, int dwn)
-{
- static struct sysconf *sc[4];
- int port = dev->id;
-
- if (!sc[port])
- sc[port] = sysconf_claim(SYS_CFG, 32, 7+port, 7+port, "USB");
- sysconf_write(sc[port], (dwn ? 1 : 0));
- return 0;
-}
-
-static int
-usb_pwr_ack(struct platform_device *dev, int host_phy, int ack)
-{
- static struct sysconf *sc[4];
- int port = dev->id;
- int i;
-
- if (!sc[port])
- sc[port] = sysconf_claim(SYS_STA, 15, 7+port, 7+port, "USB");
-
- for (i = 5; i; --i) {
- if (sysconf_read(sc[port]) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static int
-emi_pwr_dwn_req(struct platform_device *dev, int host_phy, int dwn)
-{
- static struct sysconf_field *sc;
- if (!sc)
- sc = sysconf_claim(SYS_CFG, 32, 1, 1, "emi pwr");
- sysconf_write(sc, (dwn ? 1 : 0));
- return 0;
-}
-
-static int
-emi_pwr_dwn_ack(struct platform_device *dev, int host_phy, int ack)
-{
- static struct sysconf_field *sc;
- int i;
- if (!sc)
- sc = sysconf_claim(SYS_STA, 15, 1, 1, "emi pwr ack");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static struct platform_device_pm stx7141_pm_devices[] = {
-pm_plat_dev(&emi, NULL, emi_pwr_dwn_req, emi_pwr_dwn_ack, NULL),
-pm_plat_dev(&st_usb_device[0], NULL, usb_pwr_req, usb_pwr_ack, NULL),
-pm_plat_dev(&st_usb_device[1], NULL, usb_pwr_req, usb_pwr_ack, NULL),
-pm_plat_dev(&st_usb_device[2], NULL, usb_pwr_req, usb_pwr_ack, NULL),
-pm_plat_dev(&st_usb_device[3], NULL, usb_pwr_req, usb_pwr_ack, NULL),
-};
-#endif
deleted file mode 100644
@@ -1,117 +0,0 @@
-/*
- * Platform PM Capability - STx7200
- *
- * Copyright (C) 2009 STMicroelectronics Limited
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/stm/pm.h>
-#ifdef CONFIG_PM
-static int
-usb_pwr_dwn(struct platform_device *pdev, int host_phy, int pwd)
-{
- static struct sysconf_field *sc[3];
- int port = pdev->id;
-
- /* Power up port */
- if (!sc[port])
- sc[port] = sysconf_claim(SYS_CFG, 22, 3+port, 3+port,
- "usb pwr");
- sysconf_write(sc[port], (pwd ? 1 : 0));
- return 0;
-}
-
-static int
-usb_pwr_ack(struct platform_device *pdev, int host_phy, int ack)
-{
- static struct sysconf_field *sc[3];
- int port = pdev->id;
- int i;
- if (!sc[port])
- sc[port] = sysconf_claim(SYS_STA, 13, 2+port, 2+port,
- "usb ack");
- for (i = 5; i; --i) {
- if (sysconf_read(sc[port]) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static int
-usb_sw_reset(struct platform_device *dev, int host_phy)
-{
- /* it seems there is no reset on this platform... */
- return 0;
-}
-
-static int
-emi_pwd_dwn_req(struct platform_device *pdev, int host_phy, int pwd)
-{
- static struct sysconf_field *sc;
- if (!sc)
- sc = sysconf_claim(SYS_CFG, 32, 1, 1, "emi pwr req");
-
- sysconf_write(sc, (pwd ? 1 : 0));
- return 0;
-}
-
-static int
-emi_pwd_dwn_ack(struct platform_device *pdev, int host_phy, int ack)
-{
- static struct sysconf_field *sc;
- int i;
- if (!sc)
- sc = sysconf_claim(SYS_STA, 8, 1, 1, "emi pwr ack");
- for (i = 5; i; --i) {
- if (sysconf_read(sc) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static int
-sata_pwd_dwn_req(struct platform_device *pdev, int host_phy, int pwd)
-{
- static struct sysconf_field *sc[2];
- if (cpu_data->cut_major < 3)
- return 0;
-
- if (!sc[pdev->id])
- sc[pdev->id] = sysconf_claim(SYS_CFG, 22,
- 1 + pdev->id, 1 + pdev->id, "sata");
- sysconf_write(sc[pdev->id], (pwd ? 1 : 0));
- return 0;
-}
-
-static int
-sata_pwd_dwn_ack(struct platform_device *pdev, int host_phy, int ack)
-{
- static struct sysconf_field *sc[2];
- int i;
- if (cpu_data->cut_major < 3)
- return 0;
- if (!sc[pdev->id])
- sc[pdev->id] = sysconf_claim(SYS_STA, 13,
- 0 + pdev->id, 0 + pdev->id, "sata");
- for (i = 5; i; --i) {
- if (sysconf_read(sc[pdev->id]) == ack)
- return 0;
- mdelay(10);
- }
- return -EINVAL;
-}
-
-static struct platform_device_pm stx7200_pm_devices[] = {
-pm_plat_dev(&emi, NULL, emi_pwd_dwn_req, emi_pwd_dwn_ack, NULL),
-pm_plat_dev(&st_usb[0], NULL, usb_pwr_dwn, usb_pwr_ack, usb_sw_reset),
-pm_plat_dev(&st_usb[1], NULL, usb_pwr_dwn, usb_pwr_ack, usb_sw_reset),
-pm_plat_dev(&st_usb[2], NULL, usb_pwr_dwn, usb_pwr_ack, usb_sw_reset),
-pm_plat_dev(&sata_device[0], NULL, sata_pwd_dwn_req, sata_pwd_dwn_ack, NULL),
-pm_plat_dev(&sata_device[1], NULL, sata_pwd_dwn_req, sata_pwd_dwn_ack, NULL),
-};
-#endif
deleted file mode 100644
@@ -1,52 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/soc-stb7100.h
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-#ifndef __soc_stb7100_h__
-#define __soc_stb7100_h__
-
-#define CLOCKGEN_BASE_ADDR 0x19213000 /* Clockgen A */
-#define CLOCKGENB_BASE_ADDR 0x19000000 /* Clockgen B */
-#define CLOCKGENC_BASE_ADDR 0x19210000 /* Clockgen C */
-
-#define CLKA_LOCK 0x00
-#define CLKA_PLL0 0x08
- #define CLKA_PLL0_BYPASS (1 << 20)
- #define CLKA_PLL0_ENABLE (1 << 19)
- #define CLKA_PLL0_SUSPEND ((5 << 16) | (100 << 8) | \
- (CONFIG_SH_EXTERNAL_CLOCK / 1000000))
-
-#define CLKA_PLL0_LOCK 0x10
- #define CLKA_PLL0_LOCK_LOCKED 0x01
-
-#define CLKA_ST40 0x14
-#define CLKA_ST40_IC 0x18
-#define CLKA_ST40_PER 0x1c
-#define CLKA_FDMA 0x20
-#define CLKA_PLL1 0x24
- #define CLKA_PLL1_ENABLE (1 << 19)
- #define CLKA_PLL1_SUSPEND ((5 << 16) | (100 << 8) | \
- (CONFIG_SH_EXTERNAL_CLOCK / 1000000))
-#define CLKA_PLL1_LOCK 0x2C
- #define CLKA_PLL1_LOCK_LOCKED 0x01
-
-#define CLKA_CLK_DIV 0x30
-#define CLKA_CLK_EN 0x34
- #define CLKA_CLK_EN_ST231_AUD (1 << 0)
- #define CLKA_CLK_EN_ST231_VID (1 << 1)
- #define CLKA_CLK_EN_LMI_SYS (1 << 4)
- #define CLKA_CLK_EN_LMI_VID (1 << 5)
- #define CLKA_CLK_EN_DEFAULT (CLKA_CLK_EN_ST231_AUD | \
- CLKA_CLK_EN_ST231_VID | \
- CLKA_CLK_EN_LMI_SYS | \
- CLKA_CLK_EN_LMI_VID)
-#define CLKA_PLL1_BYPASS 0x3c
-
-#endif
deleted file mode 100644
@@ -1,92 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/soc-stx5197.h
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * -------------------------------------------------------------------------
- */
-
-#ifndef __soc_stx5197_h__
-#define __soc_stx5197_h__
-
-/*
- * STx5197 Platform
- */
-enum clocks_ID {
- CLK_XTAL_ID,
- CLK_PLLA_ID,
- CLK_PLLB_ID,
- CLK_DDR_ID, /* 0 */
- CLK_LMI_ID,
- CLK_BLT_ID,
- CLK_SYS_ID,
- CLK_FDMA_ID,
- CLK_SPARE_ID,
- CLK_AV_ID, /* 6 */
- CLK_SPARE2_ID,
- CLK_ETH_ID, /* 8 */
- CLK_ST40_ID,
- CLK_ST40P_ID,
-};
-
-/* Values for mb704 */
-#define XTAL 30000000
-
-#define SYS_SERV_BASE_ADDR 0xfdc00000
-
-#define CLK_PLL_CONFIG0(x) ((x*8)+0x0)
-#define CLK_PLL_CONFIG1(x) ((x*8)+0x4)
-#define CLK_PLL_CONFIG1_POFF (1<<13)
-#define CLK_PLL_CONFIG1_LOCK (1<<15)
-
-#define CLKDIV0_CONFIG0 0x90
-#define CLKDIV1_4_CONFIG0(n) (0x0a0 + ((n-1)*0xc))
-#define CLKDIV6_10_CONFIG0(n) (0x0d0 + ((n-6)*0xc))
-
-#define CLKDIV_CONF0(x) (((x) == 0) ? CLKDIV0_CONFIG0 : ((x) < 5) ? \
- CLKDIV1_4_CONFIG0(x) : CLKDIV6_10_CONFIG0(x))
-
-#define CLKDIV_CONF1(x) (CLKDIV_CONF0(x) + 0x4)
-#define CLKDIV_CONF2(x) (CLKDIV_CONF0(x) + 0x8)
-
-
-#define CLK_MODE_CTRL 0x110
-#define CLK_MODE_CTRL_NULL 0x0
-#define CLK_MODE_CTRL_X1 0x1
-#define CLK_MODE_CTRL_PROG 0x2
-#define CLK_MODE_CTRL_STDB 0x3
-
-/*
- * The REDUCED_PM is used in CLK_MODE_CTRL_PROG...
- */
-#define CLK_REDUCED_PM_CTRL 0x114
-#define CLK_REDUCED_ON_XTAL_MEMSTDBY (1<<11)
-#define CLK_REDUCED_ON_XTAL_STDBY (~(0x22))
-
-#define CLK_LP_MODE_DIS0 0x118
-#define CLK_LP_MODE_DIS0_VALUE (0x3 << 11)
-
-#define CLK_LP_MODE_DIS2 0x11C
-
-#define CLK_DYNAMIC_PWR 0x128
-
-#define CLK_PLL_SELECT_CFG 0x180
-#define CLK_DIV_FORCE_CFG 0x184
-#define CLK_OBSERVE 0x188
-
-#define CLK_LOCK_CFG 0x300
-
-/*
- * Utility macros
- */
-#define CLK_UNLOCK() { writel(0xf0, SYS_SERV_BASE_ADDR + CLK_LOCK_CFG); \
- writel(0x0f, SYS_SERV_BASE_ADDR + CLK_LOCK_CFG); }
-
-#define CLK_LOCK() writel(0x100, SYS_SERV_BASE_ADDR + CLK_LOCK_CFG);
-
-#endif
-
deleted file mode 100644
@@ -1,48 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/soc-stx7105.h
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * -------------------------------------------------------------------------
- */
-#ifndef __soc_stx7105_h__
-#define __soc_stx7105_h__
-
-/* Values for mb680 */
-#define SYSCLKIN 30000000
-#define SYSCLKINALT 30000000
-
-#define SYSCONF_BASE_ADDR 0xfe001000
-#define CLOCKGENA_BASE_ADDR 0xfe213000 /* Clockgen A */
-#define CLOCKGENB_BASE_ADDR 0xfe000000 /* Clockgen B */
-
-/* Definitions taken from targetpack sti7105_clockgena_regs.xml */
-#define CKGA_PLL0_CFG 0x000
- #define CKGA_PLL0_CFG_DIVRES (1 << 20)
- #define CKGA_PLL0_CFG_BYPASS CKGA_PLL0_CFG_DIVRES
- #define CKGA_PLL0_CFG_LOCK (1 << 31)
-
-#define CKGA_PLL1_CFG 0x004
- #define CKGA_PLL1_CFG_DIVRES (1 << 20)
- #define CKGA_PLL1_CFG_BYPASS CKGA_PLL1_CFG_DIVRES
- #define CKGA_PLL1_CFG_LOCK (1 << 31)
-
-#define CKGA_POWER_CFG 0x010
- #define CKGA_POWER_PLL0_DISABLE 0x1
- #define CKGA_POWER_PLL1_DISABLE 0x2
-
-#define CKGA_CLKOPSRC_SWITCH_CFG(x) (0x014 + ((x) * 0x10))
-#define CKGA_CLKOBS_MUX1_CFG 0x030
-#define CKGA_CLKOBS_MUX2_CFG 0x048
-/* All the following appear to be offsets into clkgen B, despite the name */
-#define CKGA_OSC_DIV_CFG(x) (0x800 + ((x) * 4))
-#define CKGA_PLL0HS_DIV_CFG(x) (0x900 + ((x) * 4))
-#define CKGA_PLL0LS_DIV_CFG(x) (0xa10 + (((x) -4) *4))
-#define CKGA_PLL1_DIV_CFG(x) (0xb00 + ((x) *4))
-
-#endif
deleted file mode 100644
@@ -1,53 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/soc-stx7111.h
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * -------------------------------------------------------------------------
- */
-#ifndef __soc_stx7111_h__
-#define __soc_stx7111_h__
-
-/* Values for mb618 */
-#define SYSACLKIN 30000000
-#define SYSBCLKIN 30000000
-#define SYSAALTCLKIN 0
-
-#define SYSCONF_BASE_ADDR 0xfe001000
-#define CLOCKGENA_BASE_ADDR 0xfe213000 /* Clockgen A */
-#define CLOCKGENB_BASE_ADDR 0xfe000000 /* Clockgen B */
-#define CLOCKGENC_BASE_ADDR 0xfe210000 /* Clockgen C */
-
-#define CKGA_PLL0_CFG 0x000
- #define CKGA_PLL0_CFG_DIVRES (1 << 20)
- #define CKGA_PLL0_CFG_BYPASS CKGA_PLL0_CFG_DIVRES
- #define CKGA_PLL0_CFG_LOCK (1 << 31)
-
-#define CKGA_PLL1_CFG 0x004
- #define CKGA_PLL1_CFG_DIVRES (1 << 20)
- #define CKGA_PLL1_CFG_BYPASS CKGA_PLL1_CFG_DIVRES
- #define CKGA_PLL1_CFG_LOCK (1 << 31)
-
-#define CKGA_POWER_CFG 0x010
- #define CKGA_POWER_PLL0_DISABLE 0x1
- #define CKGA_POWER_PLL1_DISABLE 0x2
-
-#define CKGA_CLKOPSRC_SWITCH_CFG(x) (0x014 + ((x) * 0x10))
-
-#define CKGA_OSC_ENABLE_FB 0x0018
- #define CKGA_PLL0_ENABLE_FB 0x001c
- #define CKGA_PLL1_ENABLE_FB 0x0020
-
-#define CKGA_CLKOBS_MUX1_CFG 0x030
-#define CKGA_CLKOBS_MUX2_CFG 0x048
-
-#define CKGA_PLL0HS_DIV_CFG(x) (0x900 + ((x) * 4))
-#define CKGA_OSC_DIV_CFG(x) (0x800 + ((x) * 4))
-#define CKGA_PLL0LS_DIV_CFG(x) (0xa10 + (((x) - 4) * 4))
-#define CKGA_PLL1_DIV_CFG(x) (0xb00 + ((x) * 4))
-#endif
deleted file mode 100644
@@ -1,51 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/soc-stx7141.h
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * -------------------------------------------------------------------------
- */
-#ifndef __soc_stx7141_h__
-#define __soc_stx7141_h__
-
-/* Values for mb628 */
-#define SYSCLKIN 30000000
-#define SYSCLKINALT 30000000
-
-#define SYSCONF_BASE_ADDR 0xfe001000
-#define CLOCKGENA_BASE_ADDR 0xfe213000 /* Clockgen A */
-#define CLOCKGENB_BASE_ADDR 0xfe000000 /* Clockgen B */
-
-#define CKGA_PLL0_CFG 0x000
- #define CKGA_PLL0_CFG_DIVRES (1 << 20)
- #define CKGA_PLL0_CFG_BYPASS CKGA_PLL0_CFG_DIVRES
- #define CKGA_PLL0_CFG_LOCK (1 << 31)
-
-#define CKGA_PLL1_CFG 0x004
- #define CKGA_PLL1_CFG_DIVRES (1 << 20)
- #define CKGA_PLL1_CFG_BYPASS CKGA_PLL1_CFG_DIVRES
- #define CKGA_PLL1_CFG_LOCK (1 << 31)
-
-#define CKGA_POWER_CFG 0x010
- #define CKGA_POWER_PLL0_DISABLE 0x1
- #define CKGA_POWER_PLL1_DISABLE 0x2
-
-#define CKGA_CLKOPSRC_SWITCH_CFG(x) (0x014 + ((x) * 0x10))
-
-#define CKGA_OSC_ENABLE_FB 0x0018
-#define CKGA_PLL0_ENABLE_FB 0x001c
-#define CKGA_PLL1_ENABLE_FB 0x0020
-
-#define CKGA_CLKOBS_MUX1_CFG 0x030
-#define CKGA_CLKOBS_MUX2_CFG 0x048
-
-#define CKGA_PLL0HS_DIV_CFG(x) (0x900 + ((x) *4))
-#define CKGA_OSC_DIV_CFG(x) (0x800 + ((x) *4))
-#define CKGA_PLL0LS_DIV_CFG(x) (0xa10 + (((x)-4) *4))
-#define CKGA_PLL1_DIV_CFG(x) (0xb00 + ((x) *4))
-#endif
deleted file mode 100644
@@ -1,65 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/soc-stx7200.h
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#ifndef __soc_stx7200_h__
-#define __soc_stx7200_h__
-
-/* Values for mb519 */
-#define SYSACLKIN 27000000
-#define SYSBCLKIN 30000000
-
-#define SYSCONF_BASE_ADDR 0xfd704000
-
-#define CLOCKGEN_BASE_ADDR 0xfd700000 /* Clockgen A */
-#define CLOCKGENB_BASE_ADDR 0xfd701000 /* Clockgen B */
-#define CLOCKGENC_BASE_ADDR 0xfd601000 /* Clockgen C */
-
-#define CLKA_PLL0 0x00
-#define CLKA_PLL0_BYPASS (1 << 20)
-#define CLKA_PLL0_ENABLE_STATUS (1 << 19)
-#define CLKA_PLL0_LOCK (1 << 31)
-#define CLKA_PLL0_SUSPEND ((5 << 16) | (100 << 8) | \
- (SYSACLKIN / 1000000))
-
-#define CLKA_PLL1 0x04
-#define CLKA_PLL1_BYPASS (1 << 20)
-#define CLKA_PLL1_ENABLE_STATUS (1 << 19)
-#define CLKA_PLL1_LOCK (1 << 31)
-#define CLKA_PLL1_SUSPEND ((100 << 8) | (SYSACLKIN / 1000000))
-
-#define CLKA_PLL2 0x08
-#define CLKA_PLL2_BYPASS (1 << 20)
-#define CLKA_PLL2_ENABLE_STATUS (1 << 19)
-#define CLKA_PLL2_LOCK (1 << 31)
-#define CLKA_PLL2_SUSPEND ((5 << 16) | (100 << 8) | \
- (SYSACLKIN / 1000000))
-
-#define CKGA_CLKOUT_SEL 0x18
-
-#define CLKA_PWR_CFG 0x1C
-#define PWR_CFG_PLL0_OFF 0x1
-#define PWR_CFG_PLL1_OFF 0x2
-#define PWR_CFG_PLL2_OFF 0x4
-
-#define CLKA_DIV_CFG 0x10
-
-
-#define CLKB_PLL0_CFG 0x3C
-#define CLKB_PLL0_LOCK (1 << 31)
-#define CLKB_PLL0_BYPASS (1 << 20)
-#define CLKB_PLL0_SUSPEND ((5 << 16) | (100 << 8) | \
- (SYSACLKIN / 1000000))
-
-#define CLKB_PWR_CFG 0x58
-#define CLKB_PLL0_OFF (1 << 15)
-
-#endif
deleted file mode 100644
@@ -1,349 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/suspend-core.S
- * -------------------------------------------------------------------------
- * Copyright (C) 2008 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/linkage.h>
-#include <asm/cpu-sh4/mmu_context.h>
-#include <asm/cpu-sh4/suspend.h>
-
-/*
- * Some register are dedicated for special purpose
- */
-#define IOREGS_BASE r14
-#define ITABLE_ADDRESS r13
-#define DELAY_REG r12
-
-#define OFFSET_IOBASE 0x0
-#define OFFSET_LPJ 0x4
-#define OFFSET_DTABLE 0x8
-#define OFFSET_DTABLE_SIZE 0xc
-#define REG_INSTR r5
-#define REG_INSTR_END r6
-
-
-#define JUMPER() bra 201f; \
- nop; \
- 200: bra 200f; \
- nop; ; \
- 201:
-
-#undef ENTRY
-#define ENTRY(name, align) \
- .balign align; \
- .globl name; \
- name:
-
-.text
-ENTRY(sh4_suspend, 32) ! to be icache aligned
- bra 200f ! start the jump sequence
- nop
-sh4_really_suspend:
- mov.l r14, @-r15
- mov.l r13, @-r15
- mov.l r12, @-r15
- mov.l r11, @-r15
- mov.l r10, @-r15
- mov.l r9, @-r15
- mov.l r8, @-r15
- sts.l pr, @-r15 ! save the pr (we can call other function)
- stc.l sr, @-r15
- stc vbr, r0
-
- JUMPER()
-
- mov.l r0, @-r15 ! save the original vbr on the stack
-
- mov.l @(OFFSET_IOBASE, r4), IOREGS_BASE ! save ioregs address
- mov.l @(OFFSET_LPJ, r4), DELAY_REG
- mov REG_INSTR, ITABLE_ADDRESS ! the instruction table!
-
-/*
- * runs the suspend iteration tables
- */
- bsr do_decode
- nop
-
- cmp/eq #1, r0 ! check if we have to sleep or not
- bt __resume ! it depends if we complete the table
- ! with END or END_NO_SLEEP
-
- mova vbr_base_suspend, r0 ! this mova isn't a problem
- ! because vbr_base_suspend is
- ! 4 bytes alligned
- ldc r0, vbr ! install the wakeup_interrupt
- mov #0x3c, r1
-
- JUMPER()
-
- shll2 r1
- not r1, r1
- stc sr, r0
- and r1, r0
- ldc r0, sr ! enable the interrups
-
- sleep ! SLEEP!!!
-
-/*
- * runs the resume instruction tables
- */
-__resume:
- nop
- bsr do_decode
- nop
-
- mov.l @r15+, r0
- ldc r0, vbr ! Restore the original vbr
- mov.l @r15+, r0 ! Original sr (on interrupts disabled)
-
- JUMPER()
-
- lds.l @r15+, pr
- mov.l @r15+, r8
- mov.l @r15+, r9
- mov.l @r15+, r10
- mov.l @r15+, r11
- mov.l @r15+, r12
- mov.l @r15+, r13
- mov.l @r15+, r14
- mov.l 1f, r1
- mov.l @r1, r1 ! who waked up
- ldc r0, sr ! Restore the original sr
- rts
- mov r1, r0 ! who waked up
- JUMPER()
-
-.balign 4
-1: .long INTEVT
-
-
-.balign 1024, 0, 1024
-vbr_base_suspend:
- .long 0
-.balign 1024, 0, 1024
-
- .long 0
-.balign 512, 0, 512
-wakeup_interrupt:
- JUMPER()
- ! Disable the interrupts in the ssr
- ! and returns to the context (asap)....
- stc ssr, r0
- or #0xf0, r0
- ldc r0, ssr ! to avoit recursive irq...
- ! this means the context will be resumed
- ! with interrupt disabled!!!
-/*
- * Here we could have a problem (a sleep with interrupt disabled!!!)
- * It could happen if we detect an interrupt between
- * the enabled irq and the sleep!!!
- * Restoring the (raw) spc we will go to execute a sleep with the
- * interrupt disabled !!!!
- * To avoid that in any case we will return on the resume_address
- * label
- */
- mov.l resume_address, r0
- ldc r0, spc
- rte
- nop
-
-200:
-/*
- * load the instruction datas
- */
- mov.l resume_address, r0
- mov REG_INSTR, r0 /* start address I-table */
- mov REG_INSTR_END, r1 /* I-table size */
- tst r1, r1
-2:
- mov.l @r0, r2 /* Load the I-tables in cache */
- add #32, r0
- bf/s 2b
- dt r1
-/*
- * load the writeable datas
- */
- mov.l @(OFFSET_DTABLE, r4), r0
- mov.l @(OFFSET_DTABLE_SIZE, r4), r1
- tst r1, r1
-2:
- mov.l @r0, r2 /* Load the d-tables in cache */
- add #32, r0
- bf/s 2b
- dt r1
- bra 200f
- nop
-
-.balign 4
-resume_address: .long __resume
-
-#define SRC0 r1
-#define SRC1 r2
-#define SRC2 r3
-#define DEST r4
-#define TMP r5
-
-.balign 2
- JUMPER()
-ENTRY(do_decode, 2)
- mova suspend_jmp_table, r0
- mov r0, TMP
- mov.l @ITABLE_ADDRESS+, r0 ! opcode
- mov.l @(r0, TMP), TMP
- jmp @TMP
- nop
-
-l_end: ! OP_END
- rts ! Return point
- mov #0, r0 ! r0 = 0 to say return and sleep
-
- JUMPER()
-
-l_end_no_sleep: ! OP_END_NO_SLEEP
- rts ! Return point
- mov #1, r0 ! r0 = 1 to say return and Don't sleep
-
-l_source: ! OP_SOURCE
- mov.l @ITABLE_ADDRESS+, r0 ! load the source reg base
- mov.l @(r0, IOREGS_BASE), TMP ! load ioreg in r5
- mov.l @ITABLE_ADDRESS+, SRC0 ! load the offset
- bra do_decode
- add TMP, SRC0 ! r2 = the iomem address of source
-
- JUMPER()
-
- /* Load a @SRC0 in Dest*/
-l_load: ! #OP_LOAD
- bra do_decode
- mov.l @SRC0, DEST ! load the value
-
- /* Load a value from table in SRC0 */
-l_iload_scr0: ! OP_ILOAD_SRC0
- bra do_decode
- mov.l @ITABLE_ADDRESS+, SRC0 ! the value is in SRC0 !!!
-
- /* Load a value from table in SRC1 */
-l_iload_src1: ! OP_ILOAD_SRC1
- bra do_decode
- mov.l @ITABLE_ADDRESS+, SRC1 ! the value is in SRC1 !!!
-
- /* Load a value from table in SRC2 */
-l_iload_src2: ! OP_ILOAD_SRC2
- bra do_decode
- mov.l @ITABLE_ADDRESS+, SRC2 ! the value is in SRC2 !!!
-
- /* Load a value from table in the DEST */
-l_iload_dest: ! OP_ILOAD_DEST
- bra do_decode
- mov.l @ITABLE_ADDRESS+, DEST
-
- JUMPER()
-
- /* Store DEST value in @SRC0 */
-l_store: ! OP_STORE
- bra do_decode
- mov.l DEST, @(0,SRC0) ! store the value
-
- /* Or operation: DEST |= SRC0 */
-l_or: ! OP_OR
- bra do_decode
- or SRC0, DEST
-
- /* And operation: DEST &= SRC0 */
-l_and: ! OP_AND
- bra do_decode
- and SRC0, DEST
-
- /* Not operation: SRC0 = ~SRC1*/
- /* It's a bit dirty that the NOT operation works on SRC1 instead of DEST or SRC0*/
-l_not: ! OP_NOT
- bra do_decode
- not SRC1, SRC0
-
- JUMPER()
-
- /* While bits equal to value. This operation assumes:
- - SRC0: the iomemory address
- - SRC1: the bitmask
- - SRC2: the result
- */
-l_while_eq: ! OP_WHILE_EQ
- mov.l @SRC0, TMP
-2: and SRC1, TMP
- cmp/eq SRC2, TMP ! (@SRC0 and SRC1) ?!= SRC2)
- bt/s 2b
- mov.l @SRC0, TMP
- bra do_decode
- nop
-
- JUMPER()
- /* While bits not equal to value. This operation assumes:
- - SRC0: the iomemory address
- - SRC1: the bitmask
- - SRC2: the result
- */
-l_while_neq: ! OP_WHILE_NEQ
- mov.l @SRC0, TMP
-2: and SRC1, TMP
- cmp/eq SRC2, TMP ! (@SRC0 and SRC1) ?== SRC2)
- bf/s 2b
- mov.l @SRC0, TMP
- bra do_decode
- nop
-
- JUMPER()
-
- /* Delay operation */
-l_delay: ! OP_DELAY
- mov DELAY_REG, TMP
- tst TMP, TMP
-2:
- bf/s 2b
- dt TMP
- bra do_decode
- nop
-
- /* SCR0 = @SRC0 */
-l_load_src0: ! OP_LOAD_SRC0
- mov.l @SRC0, SRC0
- bra do_decode
- nop
-
- JUMPER()
-
-l_load_src1: ! OP_LOAD_SRC1 => SRC1 = @SRC0
- mov.l @SRC0, SRC1
- bra do_decode
- nop
-
-l_load_src2: ! OP_LOAD_SRC2 => SRC2 = @SRC0
- mov.l @SRC0, SRC2
- bra do_decode
- nop
-
-200: ! Preload the jump table
- mova suspend_jmp_table, r0
- mov r0, r1
- mov #_OPCODE_TABLE_SIZE_, r0
- cmp/eq #0, r0
-load_jtable:
- mov.l @r1, r2
- add #32, r1
- bf/s load_jtable
- dt r0
-
- bra sh4_really_suspend ! Now we jump on sh4_really_suspend
- nop ! to really suspend (and resume... ;-)
-
-.balign 32
-suspend_jmp_table:
-.long l_end, l_end_no_sleep, l_source, l_load, l_iload_scr0, l_iload_src1
-.long l_iload_src2, l_iload_dest, l_store, l_or, l_and, l_not, l_while_eq
-.long l_while_neq, l_delay, l_load_src0, l_load_src1, l_load_src2
deleted file mode 100644
@@ -1,172 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/suspend-stx5197.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/irqflags.h>
-#include <linux/stm/pm.h>
-#include <linux/stm/sysconf.h>
-#include <linux/irq.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/pm.h>
-#include <asm/irq.h>
-#include <asm/irq-ilc.h>
-
-#include "./soc-stx5197.h"
-
-#define _SYS_MON_J (0)
-#define _SYS_MON_J_MASK (1)
-#define _SYS_CFG_H (2)
-#define _SYS_CFG_H_MASK (3)
-
-
-
-/*
- * System Service Finite State Machine
- * +-------+ +------+ +------+
- * | reset |-->| X1 |<-->| Prog |
- * +-------+ +------+ +------+
- * /\ |
- * | \/
- * wakeup | +-------+
- * event +-------|Standby|
- * +-------+
- */
-
-/* *************************
- * STANDBY INSTRUCTION TABLE
- * *************************
- */
-#ifdef CONFIG_PM_DEBUG
-static unsigned long stx5197_standby_table[] __cacheline_aligned = {
-CLK_POKE(CLK_LOCK_CFG, 0xf0),
-CLK_POKE(CLK_LOCK_CFG, 0x0f), /* UnLock the clocks */
-
-CLK_POKE(CLK_MODE_CTRL, CLK_MODE_CTRL_X1),
-
-/* 1. Move all the clock on OSC */
-CLK_OR_LONG(CLK_REDUCED_PM_CTRL, CLK_REDUCED_ON_XTAL_STDBY),
-CLK_OR_LONG(CLK_PLL_CONFIG1(0), CLK_PLL_CONFIG1_POFF),
-CLK_POKE(CLK_MODE_CTRL, CLK_MODE_CTRL_PROG),
-CLK_POKE(CLK_LOCK_CFG, 0x100), /* Lock the clocks */
-/* END. */
-_END(),
-
-CLK_POKE(CLK_LOCK_CFG, 0xf0),
-CLK_POKE(CLK_LOCK_CFG, 0x0f), /* UnLock the clocks */
-CLK_POKE(CLK_MODE_CTRL, CLK_MODE_CTRL_X1),
-CLK_AND_LONG(CLK_REDUCED_PM_CTRL, ~CLK_REDUCED_ON_XTAL_STDBY),
-CLK_AND_LONG(CLK_PLL_CONFIG1(0), ~CLK_PLL_CONFIG1_POFF),
-CLK_WHILE_NEQ(CLK_PLL_CONFIG1(0), CLK_PLL_CONFIG1_LOCK, CLK_PLL_CONFIG1_LOCK),
-CLK_POKE(CLK_MODE_CTRL, CLK_MODE_CTRL_PROG),
-CLK_POKE(CLK_LOCK_CFG, 0x100), /* Lock the clocks */
-_DELAY(),
-_DELAY(),
-_DELAY(),
-_END()
-};
-#endif
-
-/* *********************
- * MEM INSTRUCTION TABLE
- * *********************
- */
-static unsigned long stx5197_mem_table[] __cacheline_aligned = {
-DATA_OR_LONG(_SYS_CFG_H, _SYS_CFG_H_MASK),
-DATA_WHILE_NEQ(_SYS_MON_J, _SYS_MON_J_MASK, _SYS_MON_J_MASK),
-
-CLK_POKE(CLK_LOCK_CFG, 0xf0),
-CLK_POKE(CLK_LOCK_CFG, 0x0f), /* UnLock the clocks */
-
-/* disable PLLs in standby */
-CLK_OR_LONG(CLK_LP_MODE_DIS0, CLK_LP_MODE_DIS0_VALUE),
-CLK_POKE(CLK_MODE_CTRL, CLK_MODE_CTRL_STDB), /* IN STANDBY */
-
-_END_NO_SLEEP(),
-/*
- * On a wakeup Event the System Service goes directly in X1 mode */
-CLK_AND_LONG(CLK_PLL_CONFIG1(0), ~CLK_PLL_CONFIG1_POFF),
-CLK_AND_LONG(CLK_PLL_CONFIG1(1), ~CLK_PLL_CONFIG1_POFF),
-/* Wait PLLs lock */
-CLK_WHILE_NEQ(CLK_PLL_CONFIG1(0), CLK_PLL_CONFIG1_LOCK, CLK_PLL_CONFIG1_LOCK),
-CLK_WHILE_NEQ(CLK_PLL_CONFIG1(1), CLK_PLL_CONFIG1_LOCK, CLK_PLL_CONFIG1_LOCK),
-
-CLK_POKE(CLK_MODE_CTRL, CLK_MODE_CTRL_PROG),
-CLK_POKE(CLK_LOCK_CFG, 0x100), /* Lock the clocks */
-
-_DELAY(),
-_DELAY(),
-DATA_AND_NOT_LONG(_SYS_CFG_H, _SYS_CFG_H_MASK),
-DATA_WHILE_EQ(_SYS_MON_J, _SYS_MON_J_MASK, _SYS_MON_J_MASK),
-
-_DELAY(),
-_DELAY(),
-_DELAY(),
-_DELAY(),
-
-_END()
-};
-
-static unsigned long stx5197_wrt_table[8] __cacheline_aligned;
-
-static int stx5197_suspend_prepare(suspend_state_t state)
-{
- return 0;
-}
-
-static unsigned long stx5197_iomem[2] __cacheline_aligned = {
- stx5197_wrt_table,
- SYS_SERV_BASE_ADDR,};
-
-static int stx5197_evt_to_irq(unsigned long evt)
-{
- return ((evt < 0x400) ? ilc2irq(evt) : evt2irq(evt));
-}
-
-static struct sh4_suspend_t st40data __cacheline_aligned = {
- .iobase = stx5197_iomem,
- .ops.prepare = stx5197_suspend_prepare,
- .evt_to_irq = stx5197_evt_to_irq,
-#ifdef CONFIG_PM_DEBUG
- .stby_tbl = (unsigned long)stx5197_standby_table,
- .stby_size = DIV_ROUND_UP(ARRAY_SIZE(stx5197_standby_table) *
- sizeof(long), L1_CACHE_BYTES),
-#endif
- .mem_tbl = (unsigned long)stx5197_mem_table,
- .mem_size = DIV_ROUND_UP(ARRAY_SIZE(stx5197_mem_table) * sizeof(long),
- L1_CACHE_BYTES),
- .wrt_tbl = (unsigned long)stx5197_wrt_table,
- .wrt_size = DIV_ROUND_UP(ARRAY_SIZE(stx5197_wrt_table) * sizeof(long),
- L1_CACHE_BYTES),
-};
-
-static int __init suspend_platform_setup(void)
-{
-
- struct sysconf_field* sc;
-
- sc = sysconf_claim(CFG_MONITOR_J, 24, 24, "LMI pwd ack");
- stx5197_wrt_table[_SYS_MON_J] = (unsigned long)sysconf_address(sc);
- stx5197_wrt_table[_SYS_MON_J_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(CFG_CTRL_H, 26, 26, "LMI pwd req");
- stx5197_wrt_table[_SYS_CFG_H] = (unsigned long)sysconf_address(sc);
- stx5197_wrt_table[_SYS_CFG_H_MASK] = sysconf_mask(sc);
-
- return sh4_suspend_register(&st40data);
-}
-
-late_initcall(suspend_platform_setup);
deleted file mode 100644
@@ -1,253 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/suspend-stb7100.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/irqflags.h>
-#include <linux/stm/sysconf.h>
-#include <linux/stm/pm.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/pm.h>
-
-#include "./soc-stb7100.h"
-
-#define _SYS_STA12 (2)
-#define _SYS_STA12_MASK (3)
-#define _SYS_STA13 (4)
-#define _SYS_STA13_MASK (5)
-#define _SYS_CFG11 (6)
-#define _SYS_CFG11_MASK (7)
-
-extern void __iomem *clkgena_base;
-
-/* *************************
- * STANDBY INSTRUCTION TABLE
- * *************************
- */
-#ifdef CONFIG_PM_DEBUG
-static unsigned long stb7100_standby_table[] __cacheline_aligned = {
-/* 1. PLL0 at the minimum frequency */
- /* Unlock the clocks */
-CLK_POKE(CLKA_LOCK, 0xc0de),
- /* enables the bypass */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS),
- /* disable the pll0 */
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_ENABLE)),
- /* set to zero mdiv ndiv pdiv */
-CLK_AND_LONG(CLKA_PLL0, ~(0x7ffff)),
- /* set new mdiv ndiv pdiv */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_SUSPEND),
- /* enables the pll0 */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_ENABLE),
- /* Wait PLL0 lock */
-CLK_WHILE_NEQ(CLKA_PLL0_LOCK, CLKA_PLL0_LOCK_LOCKED, CLKA_PLL0_LOCK_LOCKED),
- /* removes the bypass */
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)),
- /* 0 4 5 - 1:4 1:6 1:8 */
- /* 3 4 5 - 1:4 1:6 1:8 */
- /* 1 2 3 - 1:2 1:3 1:4 */
-CLK_POKE(CLKA_ST40_PER, 0x5),
-CLK_POKE(CLKA_ST40_IC, 0x5),
-CLK_POKE(CLKA_ST40, 0x3),
-/* END. */
-_END(),
-
-/* 1. Restore the highest frequency cpu/bus/per ratios */
-CLK_POKE(CLKA_ST40, 0x0),
-CLK_POKE(CLKA_ST40_IC, 0x1),
-CLK_POKE(CLKA_ST40_PER, 0x0),
-
-/* 2. PLL0 at the standard frequency */
- /* enables bypass */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS),
- /* disables the pll0 */
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_ENABLE)),
-DATA_LOAD(0x0),
-IMMEDIATE_SRC0(CLKA_PLL0_BYPASS),
-_OR(),
- /* save the current r2 in PLL0 */
-CLK_STORE(CLKA_PLL0),
- /* enables the pll0 */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_ENABLE),
- /* Wait PLL0 lock */
-CLK_WHILE_NEQ(CLKA_PLL0_LOCK, CLKA_PLL0_LOCK_LOCKED, CLKA_PLL0_LOCK_LOCKED),
- /* removes the bypass */
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)),
- /* Lock the clocks */
-CLK_POKE(CLKA_LOCK, 0x0),
-/* END. */
-_END()
-};
-#endif
-/* *********************
- * MEM INSTRUCTION TABLE
- * *********************
- */
-static unsigned long stb7100_mem_table[] __cacheline_aligned = {
-/* 1. Enables the DDR self refresh mode */
-DATA_OR_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
- /* waits until the ack bit is zero */
-DATA_WHILE_NEQ(_SYS_STA12, _SYS_STA12_MASK, _SYS_STA12_MASK),
- /* waits until the ack bit is zero */
-DATA_WHILE_NEQ(_SYS_STA13, _SYS_STA13_MASK, _SYS_STA13_MASK),
-
-/* 2. PLL0 at the minimum frequency */
- /* unlock the clocks */
-CLK_POKE(CLKA_LOCK, 0xc0de),
- /* enables the bypass */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS),
- /* disable the pll0 */
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_ENABLE)),
- /* set to zero mdiv ndiv pdiv */
-CLK_AND_LONG(CLKA_PLL0, ~(0x7ffff)),
- /* set new mdiv ndiv pdiv */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_SUSPEND),
- /* enables the pll0 */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_ENABLE),
- /* Wait PLL0 lock */
-CLK_WHILE_NEQ(CLKA_PLL0_LOCK, CLKA_PLL0_LOCK_LOCKED, CLKA_PLL0_LOCK_LOCKED),
- /* removes the bypass */
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)),
-
-/* 3. PLL1 at the minimum frequency */
- /* enables the bypass */
-CLK_OR_LONG(CLKA_PLL1_BYPASS, 2),
- /* disable the pll1 */
-CLK_AND_LONG(CLKA_PLL1, ~(CLKA_PLL1_ENABLE)),
- /* set to zero mdiv ndiv pdiv */
-CLK_AND_LONG(CLKA_PLL1, ~(0x7ffff)),
- /* set new mdiv ndiv pdiv */
-CLK_OR_LONG(CLKA_PLL1, CLKA_PLL1_SUSPEND),
- /* enables the pll1 */
-CLK_OR_LONG(CLKA_PLL1, CLKA_PLL1_ENABLE),
- /* Wait PLL1 lock */
-CLK_WHILE_NEQ(CLKA_PLL1_LOCK, CLKA_PLL1_LOCK_LOCKED, CLKA_PLL1_LOCK_LOCKED),
-CLK_AND_LONG(CLKA_PLL1_BYPASS, ~(2)), /* removes the bypass */
-
-/* 4. Turn-off the LMI clocks and the ST231 clocks */
-CLK_AND_LONG(CLKA_CLK_EN, ~(CLKA_CLK_EN_DEFAULT)),
-CLK_POKE(CLKA_ST40_PER, 0x5), /* 0 4 5 - 1:4 1:6 1:8 */
-CLK_POKE(CLKA_ST40_IC, 0x5), /* 3 4 5 - 1:4 1:6 1:8 */
-CLK_POKE(CLKA_ST40, 0x3), /* 1 2 3 - 1:2 1:3 1:4 */
- /* END. */
-_END(),
-
-/* 1. Restore the highest frequency cpu/bus/per ratios */
-CLK_POKE(CLKA_ST40, 0x0),
-CLK_POKE(CLKA_ST40_IC, 0x1),
-CLK_POKE(CLKA_ST40_PER, 0x0),
-
-/* 2. Turn-on the LMI clocks and the ST231 clocks*/
-CLK_OR_LONG(CLKA_CLK_EN, CLKA_CLK_EN_DEFAULT),
-
-/* 3. PLL1 at the standard frequency */
-CLK_OR_LONG(CLKA_PLL1_BYPASS, 2), /* enables the bypass */
-CLK_AND_LONG(CLKA_PLL1, ~(CLKA_PLL1_ENABLE)), /* disable the pll1 */
-DATA_LOAD(0x1),
-CLK_STORE(CLKA_PLL1),
-CLK_OR_LONG(CLKA_PLL1, CLKA_PLL1_ENABLE), /* enables the pll1 */
- /* Wait PLL1 lock */
-CLK_WHILE_NEQ(CLKA_PLL1_LOCK, CLKA_PLL1_LOCK_LOCKED, CLKA_PLL1_LOCK_LOCKED),
-CLK_AND_LONG(CLKA_PLL1_BYPASS, ~(2)), /* removes the bypass */
-
-/* 4. Disables the DDR self refresh mode */
-DATA_AND_NOT_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
-
-/* wait until theack bit is high */
-DATA_WHILE_EQ(_SYS_STA12, _SYS_STA12_MASK, _SYS_STA12_MASK),
-DATA_WHILE_EQ(_SYS_STA13, _SYS_STA13_MASK, _SYS_STA12_MASK),
-
-/* 5. PLL0 at the standard frequency */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS), /* enables bypass */
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_ENABLE)), /* disables the pll0 */
-DATA_LOAD(0x0),
-IMMEDIATE_SRC0(CLKA_PLL0_BYPASS),
-_OR(),
-CLK_STORE(CLKA_PLL0), /* save the r2 in PLL0 */
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_ENABLE), /* enables the pll0 */
- /* Wait PLL0 lock */
-CLK_WHILE_NEQ(CLKA_PLL0_LOCK, CLKA_PLL0_LOCK_LOCKED, CLKA_PLL0_LOCK_LOCKED),
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)), /* removes the bypass */
-CLK_POKE(CLKA_LOCK, 0x0),
-
-/* Lock the clocks */
-_DELAY(),
-_DELAY(),
-_DELAY(),
-/* END. */
-_END()
-};
-
-static unsigned long stb7100_wrt_table[8] __cacheline_aligned;
-
-static int stb7100_suspend_prepare(suspend_state_t state)
-{
- stb7100_wrt_table[0] = readl(clkgena_base + CLKA_PLL0) & 0x7ffff;
- stb7100_wrt_table[1] = readl(clkgena_base + CLKA_PLL1) & 0x7ffff;
- return 0;
-}
-
-static int stb7100_evttoirq(unsigned long evt)
-{
- return evt2irq(evt);
-}
-
-static unsigned long stb7100_iomem[2] __cacheline_aligned = {
- stb7100_wrt_table,
-};
-
-static struct sh4_suspend_t st40data __cacheline_aligned = {
- .iobase = stb7100_iomem,
- .ops.prepare = stb7100_suspend_prepare,
- .evt_to_irq = stb7100_evttoirq,
-#ifdef CONFIG_PM_DEBUG
- .stby_tbl = (unsigned long)stb7100_standby_table,
- .stby_size = DIV_ROUND_UP(ARRAY_SIZE(stb7100_standby_table) *
- sizeof(long), L1_CACHE_BYTES),
-#endif
- .mem_tbl = (unsigned long)stb7100_mem_table,
- .mem_size = DIV_ROUND_UP(ARRAY_SIZE(stb7100_mem_table) * sizeof(long),
- L1_CACHE_BYTES),
- .wrt_tbl = (unsigned long)stb7100_wrt_table,
- .wrt_size = DIV_ROUND_UP(ARRAY_SIZE(stb7100_wrt_table) * sizeof(long),
- L1_CACHE_BYTES),
-};
-
-static int __init suspend_platform_setup()
-{
- struct sysconf_field* sc;
-
- stb7100_iomem[1] = (unsigned long) clkgena_base;
-
- sc = sysconf_claim(SYS_STA, 12, 28, 28, "pm");
- stb7100_wrt_table[_SYS_STA12] = (unsigned long)sysconf_address(sc);
- stb7100_wrt_table[_SYS_STA12_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 13, 28, 28, "pm");
- stb7100_wrt_table[_SYS_STA13] = (unsigned long)sysconf_address(sc);
- stb7100_wrt_table[_SYS_STA13_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_CFG, 11, 28, 28, "pm");
- stb7100_wrt_table[_SYS_CFG11] = (unsigned long)sysconf_address(sc);
- stb7100_wrt_table[_SYS_CFG11_MASK] = sysconf_mask(sc);
- sc = sysconf_claim(SYS_CFG, 11, 30, 30, "pm");
- stb7100_wrt_table[_SYS_CFG11_MASK] |= sysconf_mask(sc);
-
- return sh4_suspend_register(&st40data);
-}
-
-late_initcall(suspend_platform_setup);
deleted file mode 100644
@@ -1,212 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/suspend-stx7105.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/irqflags.h>
-#include <linux/stm/pm.h>
-#include <linux/stm/sysconf.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/pm.h>
-#include <asm/irq.h>
-
-#include "./soc-stx7105.h"
-
-#define _SYS_STA4 (7)
-#define _SYS_STA4_MASK (8)
-#define _SYS_STA3 (11)
-#define _SYS_STA3_MASK (12)
-#define _SYS_STA3_VALUE (13)
-
-#define _SYS_CFG11 (9)
-#define _SYS_CFG11_MASK (10)
-#define _SYS_CFG38 (5)
-#define _SYS_CFG38_MASK (6)
-/* *************************
- * STANDBY INSTRUCTION TABLE
- * *************************
- */
-#ifdef CONFIG_PM_DEBUG
-static unsigned long stx7105_standby_table[] __cacheline_aligned = {
-/* 1. Move all the clock on OSC */
-CLK_POKE(CKGA_CLKOPSRC_SWITCH_CFG(0x0), 0x0),
-CLK_POKE(CKGA_OSC_DIV_CFG(0x5), 29), /* ic_if_100 @ 1 MHz to be safe for Lirc*/
-
-IMMEDIATE_DEST(0x1f),
-/* reduces OSC_st40 */
-CLK_STORE(CKGA_OSC_DIV_CFG(4)),
-/* reduces OSC_clk_ic */
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-/* END. */
-_END(),
-
-DATA_LOAD(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-DATA_LOAD(0x1),
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-DATA_LOAD(0x2),
-CLK_STORE(CKGA_OSC_DIV_CFG(5)),
-/* END. */
-_END()
-};
-#endif
-/* *********************
- * MEM INSTRUCTION TABLE
- * *********************
- */
-static unsigned long stx7105_mem_table[] __cacheline_aligned = {
-/* 1. Enables the DDR self refresh mode */
-DATA_OR_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-/* waits until the ack bit is zero */
-DATA_WHILE_NEQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-/* 1.1 Turn-off the ClockGenD */
-DATA_OR_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
-
-IMMEDIATE_DEST(0x1f),
-/* reduces OSC_st40 */
-CLK_STORE(CKGA_OSC_DIV_CFG(4)),
-/* reduces OSC_clk_ic */
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-/* reduces OSC_clk_ic_if_200 */
-CLK_STORE(CKGA_OSC_DIV_CFG(17)),
-/* 2. Move all the clock on OSC */
-
-CLK_POKE(CKGA_OSC_DIV_CFG(5), 29), /* ic_if_100 @ 1MHz to be safe for Lirc*/
-
-IMMEDIATE_DEST(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x1)),
-/* PLLs in power down */
-CLK_OR_LONG(CKGA_POWER_CFG, 0x3),
- /* END. */
-_END(),
-
-/* Turn-on the PLLs */
-CLK_AND_LONG(CKGA_POWER_CFG, ~3),
-/* Wait PLLS lock */
-CLK_WHILE_NEQ(CKGA_PLL0_CFG, CKGA_PLL0_CFG_LOCK, CKGA_PLL0_CFG_LOCK),
-CLK_WHILE_NEQ(CKGA_PLL1_CFG, CKGA_PLL1_CFG_LOCK, CKGA_PLL1_CFG_LOCK),
-
-/* 1. Turn-on the LMI ClocksGenD */
-DATA_AND_NOT_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
-/* Wait LMI ClocksGenD lock */
-DATA_WHILE_NEQ(_SYS_STA3, _SYS_STA3_MASK, _SYS_STA3_VALUE),
-
-/* 2. Disables the DDR self refresh mode */
-DATA_AND_NOT_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-/* waits until the ack bit is zero */
-DATA_WHILE_EQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-
-IMMEDIATE_DEST(0x10000),
-CLK_STORE(CKGA_PLL0LS_DIV_CFG(4)),
-
-/* 3. Restore the previous clocks setting */
-DATA_LOAD(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-DATA_LOAD(0x1),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x1)),
-DATA_LOAD(0x3),
-CLK_STORE(CKGA_OSC_DIV_CFG(5)),
-DATA_LOAD(0x2),
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-DATA_LOAD(0x4),
-CLK_STORE(CKGA_OSC_DIV_CFG(17)),
-
-_DELAY(),
-_DELAY(),
-_DELAY(),
-_END()
-};
-
-static unsigned long stx7105_wrt_table[16] __cacheline_aligned;
-
-static int stx7105_suspend_prepare(suspend_state_t state)
-{
-#ifdef CONFIG_PM_DEBUG
- if (state == PM_SUSPEND_STANDBY) {
- stx7105_wrt_table[0] = /* swith config */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
- stx7105_wrt_table[1] = /* clk_STNoc */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
- stx7105_wrt_table[2] = /* clk_ic_if_100 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(5));
- } else
-#endif
- {
- stx7105_wrt_table[0] = /* swith config */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
- stx7105_wrt_table[1] = /* swith config 1 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(1));
- stx7105_wrt_table[2] = /* clk_STNoc */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
- stx7105_wrt_table[3] = /* clk_ic_if_100 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(5));
- stx7105_wrt_table[4] = /* clk_ic_if_200 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(17));
- }
- return 0;
-}
-
-static unsigned long stx7105_iomem[2] __cacheline_aligned = {
- stx7105_wrt_table,
- CLOCKGENA_BASE_ADDR};
-
-static int stx7105_evt_to_irq(unsigned long evt)
-{
- return evt2irq(evt);
-}
-
-static struct sh4_suspend_t st40data __cacheline_aligned = {
- .iobase = stx7105_iomem,
- .ops.prepare = stx7105_suspend_prepare,
- .evt_to_irq = stx7105_evt_to_irq,
-#ifdef CONFIG_PM_DEBUG
- .stby_tbl = (unsigned long)stx7105_standby_table,
- .stby_size = DIV_ROUND_UP(ARRAY_SIZE(stx7105_standby_table) *
- sizeof(long), L1_CACHE_BYTES),
-#endif
- .mem_tbl = (unsigned long)stx7105_mem_table,
- .mem_size = DIV_ROUND_UP(ARRAY_SIZE(stx7105_mem_table) * sizeof(long),
- L1_CACHE_BYTES),
- .wrt_tbl = (unsigned long)stx7105_wrt_table,
- .wrt_size = DIV_ROUND_UP(ARRAY_SIZE(stx7105_wrt_table) * sizeof(long),
- L1_CACHE_BYTES),
-};
-
-static int __init suspend_platform_setup(void)
-{
-
- struct sysconf_field* sc;
- sc = sysconf_claim(SYS_CFG, 38, 20, 20, "pm");
- stx7105_wrt_table[_SYS_CFG38] = (unsigned long)sysconf_address(sc);
- stx7105_wrt_table[_SYS_CFG38_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_CFG, 11, 12, 12, "pm");
- stx7105_wrt_table[_SYS_CFG11] = (unsigned long)sysconf_address(sc);
- stx7105_wrt_table[_SYS_CFG11_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 4, 0, 0, "pm");
- stx7105_wrt_table[_SYS_STA4] = (unsigned long)sysconf_address(sc);
- stx7105_wrt_table[_SYS_STA4_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 3, 0, 0, "pm");
- stx7105_wrt_table[_SYS_STA3] = (unsigned long)sysconf_address(sc);
- stx7105_wrt_table[_SYS_STA3_MASK] = sysconf_mask(sc);
- stx7105_wrt_table[_SYS_STA3_VALUE] = 0;
- return sh4_suspend_register(&st40data);
-}
-
-late_initcall(suspend_platform_setup);
deleted file mode 100644
@@ -1,222 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/suspend-stx7111.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/irqflags.h>
-#include <linux/stm/sysconf.h>
-#include <linux/stm/pm.h>
-#include <linux/irq.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/pm.h>
-#include <asm/irq-ilc.h>
-
-#include "./soc-stx7111.h"
-
-#define _SYS_STA4 (5)
-#define _SYS_STA4_MASK (6)
-#define _SYS_STA3 (11)
-#define _SYS_STA3_MASK (12)
-#define _SYS_STA3_VALUE (13)
-
-#define _SYS_CFG11 (7)
-#define _SYS_CFG11_MASK (8)
-
-#define _SYS_CFG38 (9)
-#define _SYS_CFG38_MASK (10)
-
-/* *************************
- * STANDBY INSTRUCTION TABLE
- * *************************
- */
-#ifdef CONFIG_PM_DEBUG
-static unsigned long stx7111_standby_table[] __cacheline_aligned = {
-/* 1. Move all the clock on OSC */
-CLK_POKE(CKGA_CLKOPSRC_SWITCH_CFG(0x0), 0x0),
-CLK_POKE(CKGA_OSC_DIV_CFG(5), 29), /* clk_ic_if_100 @ 1 MHz to be safe for lirc */
-
-IMMEDIATE_DEST(0x1f),
-/* reduces the st40 frequency */
-CLK_STORE(CKGA_OSC_DIV_CFG(4)),
-/* reduces the clk_STNoc_ic */
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-
- /* END. */
-_END(),
-
-IMMEDIATE_DEST(0x10000),
-CLK_STORE(CKGA_PLL0LS_DIV_CFG(4)),
-DATA_LOAD(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-DATA_LOAD(0x1),
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-DATA_LOAD(0x2),
-CLK_STORE(CKGA_OSC_DIV_CFG(5)),
-
- /* END. */
-_END()
-};
-#endif
-
-/* *********************
- * MEM INSTRUCTION TABLE
- * *********************
- */
-static unsigned long stx7111_mem_table[] __cacheline_aligned = {
-/* 1. Enables the DDR self refresh mode */
-DATA_OR_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-/* waits until the ack bit is zero */
-DATA_WHILE_NEQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-/* 1.1 Turn-off the ClockGenD */
-DATA_OR_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
-
-IMMEDIATE_DEST(0x1f),
-CLK_STORE(CKGA_OSC_DIV_CFG(4)), /* reduces the st40 frequency */
-CLK_STORE(CKGA_OSC_DIV_CFG(17)), /* reduces the clk_ic_if_200 */
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)), /* reduces the clk_STNoc_ic */
-
-CLK_POKE(CKGA_OSC_DIV_CFG(5), 29), /* clk_ic_if_100 @ 1 MHz to be safe for lirc */
-
-/* 2. Move all the clock on OSC */
-IMMEDIATE_DEST(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x1)),
-
-/* PLLs in power down */
-CLK_OR_LONG(CKGA_POWER_CFG, 0x3),
- /* END. */
-_END(),
-
-/* Turn-on the PLLs */
-CLK_AND_LONG(CKGA_POWER_CFG, ~3),
-/* Wait PLLs lock */
-CLK_WHILE_NEQ(CKGA_PLL0_CFG, CKGA_PLL0_CFG_LOCK, CKGA_PLL0_CFG_LOCK),
-CLK_WHILE_NEQ(CKGA_PLL1_CFG, CKGA_PLL1_CFG_LOCK, CKGA_PLL1_CFG_LOCK),
-
-/* 1. Turn-on the LMI ClocksGenD */
-DATA_AND_NOT_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
-/* Wait LMI ClocksGenD lock */
-DATA_WHILE_NEQ(_SYS_STA3, _SYS_STA3_MASK, _SYS_STA3_VALUE),
-
-/* 2. Disables the DDR self refresh mode */
-DATA_AND_NOT_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-/* waits until the ack bit is zero */
-DATA_WHILE_EQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-
-
-IMMEDIATE_DEST(0x10000),
-/* 3. Restore the previous clocks setting */
-CLK_STORE(CKGA_OSC_DIV_CFG(4)),
-DATA_LOAD(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-DATA_LOAD(0x1),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x1)),
-DATA_LOAD(0x2),
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-DATA_LOAD(0x3),
-CLK_STORE(CKGA_OSC_DIV_CFG(5)),
-DATA_LOAD(0x4),
-CLK_STORE(CKGA_OSC_DIV_CFG(17)),
-
-_DELAY(),
-_DELAY(),
-_DELAY(),
-_END()
-};
-
-static unsigned long stx7111_wrt_table[16] __cacheline_aligned;
-
-static int stx7111_suspend_prepare(suspend_state_t state)
-{
-#ifdef CONFIG_PM_DEBUG
- if (state == PM_SUSPEND_STANDBY) {
- stx7111_wrt_table[0] = /* swith config */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
- stx7111_wrt_table[1] = /* clk_STNoc_ic */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
- stx7111_wrt_table[2] = /* clk_ic_if_100 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(5));
- } else
-#endif
- {
- stx7111_wrt_table[0] = /* swith config */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
- stx7111_wrt_table[1] = /* swith config 1 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(1));
- stx7111_wrt_table[2] = /* clk_STNoc_ic */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
- stx7111_wrt_table[3] = /* clk_ic_if_100 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(5));
- stx7111_wrt_table[4] = /* clk_ic_if_200 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(17));
- }
- return 0;
-}
-
-static unsigned long stx7111_iomem[2] __cacheline_aligned = {
- stx7111_wrt_table,
- CLOCKGENA_BASE_ADDR};
-
-static int stx7111_evttoirq(unsigned long evt)
-{
- return evt2irq(evt);
-}
-
-static struct sh4_suspend_t st40data __cacheline_aligned = {
- .iobase = stx7111_iomem,
- .ops.prepare = stx7111_suspend_prepare,
- .evt_to_irq = stx7111_evttoirq,
-#ifdef CONFIG_PM_DEBUG
- .stby_tbl = (unsigned long)stx7111_standby_table,
- .stby_size = DIV_ROUND_UP(ARRAY_SIZE(stx7111_standby_table) *
- sizeof(long), L1_CACHE_BYTES),
-#endif
- .mem_tbl = (unsigned long)stx7111_mem_table,
- .mem_size = DIV_ROUND_UP(ARRAY_SIZE(stx7111_mem_table) * sizeof(long),
- L1_CACHE_BYTES),
- .wrt_tbl = (unsigned long)stx7111_wrt_table,
- .wrt_size = DIV_ROUND_UP(ARRAY_SIZE(stx7111_wrt_table) * sizeof(long),
- L1_CACHE_BYTES),
-};
-
-static int __init suspend_platform_setup()
-{
- struct sysconf_field* sc;
-#ifdef CONFIG_PM_DEBUG
-/* route the sh4/2 clock frequenfy */
- iowrite32(0xc, CLOCKGENA_BASE_ADDR + CKGA_CLKOBS_MUX1_CFG);
-#endif
-
- sc = sysconf_claim(SYS_CFG, 38, 20, 20, "pm");
- stx7111_wrt_table[_SYS_CFG38] = (unsigned long)sysconf_address(sc);
- stx7111_wrt_table[_SYS_CFG38_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_CFG, 11, 12, 12, "pm");
- stx7111_wrt_table[_SYS_CFG11] = (unsigned long)sysconf_address(sc);
- stx7111_wrt_table[_SYS_CFG11_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 4, 0, 0, "pm");
- stx7111_wrt_table[_SYS_STA4] = (unsigned long)sysconf_address(sc);
- stx7111_wrt_table[_SYS_STA4_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 3, 0, 0, "pm");
- stx7111_wrt_table[_SYS_STA3] = (unsigned long)sysconf_address(sc);
- stx7111_wrt_table[_SYS_STA3_MASK] = sysconf_mask(sc);
- stx7111_wrt_table[_SYS_STA3_VALUE] = 0;
- return sh4_suspend_register(&st40data);
-}
-
-late_initcall(suspend_platform_setup);
deleted file mode 100644
@@ -1,235 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/suspend-stx7141.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/irqflags.h>
-#include <linux/stm/pm.h>
-#include <linux/stm/sysconf.h>
-#include <linux/irq.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/pm.h>
-#include <asm/irq-ilc.h>
-
-#ifdef CONFIG_PM_DEBUG
-#include <linux/stm/pio.h>
-#endif
-
-#include "./soc-stx7141.h"
-
-#define _SYS_STA4 (7)
-#define _SYS_STA4_MASK (8)
-#define _SYS_STA3 (11)
-#define _SYS_STA3_MASK (12)
-#define _SYS_STA3_VALUE (13)
-
-#define _SYS_CFG11 (9)
-#define _SYS_CFG11_MASK (10)
-#define _SYS_CFG38 (5)
-#define _SYS_CFG38_MASK (6)
-
-/* *************************
- * STANDBY INSTRUCTION TABLE
- * *************************
- */
-#ifdef CONFIG_PM_DEBUG
-static unsigned long stx7141_standby_table[] __cacheline_aligned = {
-IMMEDIATE_DEST(0x1f),
-/* reduces the st40 frequency */
-CLK_STORE(CKGA_OSC_DIV_CFG(4)),
-/* reduces the clk_ic */
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-
-CLK_POKE(CKGA_OSC_DIV_CFG(10), 29),/* clk_ic_if_100 @ 1 MHz to be safe for lirc */
-/* 2. Move all the clock on OSC */
-CLK_POKE(CKGA_CLKOPSRC_SWITCH_CFG(0x0), 0),
-
- /* END. */
-_END(),
-
-DATA_LOAD(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-DATA_LOAD(0x1),
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-DATA_LOAD(0x2),
-CLK_STORE(CKGA_OSC_DIV_CFG(10)),
- /* END. */
-_END()
-};
-#endif
-
-/* *********************
- * MEM INSTRUCTION TABLE
- * *********************
- */
-static unsigned long stx7141_mem_table[] __cacheline_aligned = {
-/* 1. Enables the DDR self refresh mode */
-DATA_OR_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-/* waits until the ack bit is zero */
-DATA_WHILE_NEQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-/* 1.1 Turn-off the ClockGenD */
-DATA_OR_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
-
-IMMEDIATE_DEST(0x1f),
-/* reduces OSC_st40 */
-CLK_STORE(CKGA_OSC_DIV_CFG(4)),
-/* reduces OSC_clk_ic */
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-/* reduces OSC_clk_ic_if_200 */
-CLK_STORE(CKGA_OSC_DIV_CFG(17)),
-
-CLK_POKE(CKGA_OSC_DIV_CFG(10), 29),/* clk_ic_if_100 @ 1 MHz to be safe for lirc */
-/* 2. Move all the clock on OSC */
-IMMEDIATE_DEST(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x1)),
-/* PLLs in power down */
-CLK_OR_LONG(CKGA_POWER_CFG, 0x3),
- /* END. */
-_END(),
-
-/* Turn-on the PLLs */
-CLK_AND_LONG(CKGA_POWER_CFG, ~3),
-/* Wait PLLs lock */
-CLK_WHILE_NEQ(CKGA_PLL0_CFG, CKGA_PLL0_CFG_LOCK, CKGA_PLL0_CFG_LOCK),
-CLK_WHILE_NEQ(CKGA_PLL1_CFG, CKGA_PLL1_CFG_LOCK, CKGA_PLL1_CFG_LOCK),
-
-/* 1. Turn-on the LMI ClocksGenD */
-DATA_AND_NOT_LONG(_SYS_CFG11, _SYS_CFG11_MASK),
-/* Wait LMI ClocksGenD lock */
-DATA_WHILE_NEQ(_SYS_STA3, _SYS_STA3_MASK, _SYS_STA3_VALUE),
-
-/* 2. Disables the DDR self refresh mode */
-DATA_AND_NOT_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-/* waits until the ack bit is zero */
-DATA_WHILE_EQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-
-DATA_LOAD(0x0),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
-DATA_LOAD(0x1),
-CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x1)),
-
-DATA_LOAD(0x2),
-CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
-
-DATA_LOAD(0x3),
-CLK_STORE(CKGA_OSC_DIV_CFG(10)),
-
-DATA_LOAD(0x4),
-CLK_STORE(CKGA_OSC_DIV_CFG(17)),
-_DELAY(),
-_DELAY(),
-_DELAY(),
-_END()
-};
-
-static unsigned long stx7141_wrt_table[16] __cacheline_aligned;
-
-static int stx7141_suspend_prepare(suspend_state_t state)
-{
-#ifdef CONFIG_PM_DEBUG
- if (state == PM_SUSPEND_STANDBY) {
- stx7141_wrt_table[0] = /* swith config */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
- stx7141_wrt_table[1] = /* clk_ic */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
- stx7141_wrt_table[2] = /* clk_ic_if_100 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(10));
- } else
-#endif
- {
- stx7141_wrt_table[0] = /* swith config */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
- stx7141_wrt_table[1] = /* swith config */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(1));
- stx7141_wrt_table[2] = /* clk_ic */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
- stx7141_wrt_table[3] = /* clk_ic_if_100 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(10));
- stx7141_wrt_table[4] = /* clk_ic_if_200 */
- ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(17));
- }
- return 0;
-}
-
-static unsigned long stx7141_iomem[2] __cacheline_aligned = {
- stx7141_wrt_table,
- CLOCKGENA_BASE_ADDR};
-
-static int stx7141_evttoirq(unsigned long evt)
-{
- return ((evt < 0x400) ? ilc2irq(evt) : evt2irq(evt));
-}
-
-static struct sh4_suspend_t st40data __cacheline_aligned = {
- .iobase = stx7141_iomem,
- .ops.prepare = stx7141_suspend_prepare,
- .evt_to_irq = stx7141_evttoirq,
-#ifdef CONFIG_PM_DEBUG
- .stby_tbl = (unsigned long)stx7141_standby_table,
- .stby_size = DIV_ROUND_UP(ARRAY_SIZE(stx7141_standby_table) *
- sizeof(long), L1_CACHE_BYTES),
-#endif
- .mem_tbl = (unsigned long)stx7141_mem_table,
- .mem_size = DIV_ROUND_UP(ARRAY_SIZE(stx7141_mem_table) * sizeof(long),
- L1_CACHE_BYTES),
- .wrt_tbl = (unsigned long)stx7141_wrt_table,
- .wrt_size = DIV_ROUND_UP(ARRAY_SIZE(stx7141_wrt_table) * sizeof(long),
- L1_CACHE_BYTES),
-};
-
-static int __init suspend_platform_setup()
-{
- struct sysconf_field *sc;
-#if defined(CONFIG_PM_DEBUG)
- struct stpio_pin *pin;
- /* route the sh4/2 clock frequenfy */
- pin = stpio_request_set_pin(3, 2, "clkA dbg", STPIO_ALT_OUT, 1);
- if (pin) {
- iowrite32(0xc, CLOCKGENA_BASE_ADDR + CKGA_CLKOBS_MUX1_CFG);
- sc = sysconf_claim(SYS_CFG, 19, 22, 23, "clkA dbg");
- if (sc)
- sysconf_write(sc, 11);
- else {
- printk(KERN_ERR
- "Not able to acquire the sysconf 19 [22,23]\n");
- stpio_free_pin(pin);
- }
- } else
- printk(KERN_ERR
- "Not able to route the ClkA on external pin\n");
-#endif
-
- sc = sysconf_claim(SYS_CFG, 38, 20, 20, "pm");
- stx7141_wrt_table[_SYS_CFG38] = (unsigned long)sysconf_address(sc);
- stx7141_wrt_table[_SYS_CFG38_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_CFG, 11, 12, 12, "pm");
- stx7141_wrt_table[_SYS_CFG11] = (unsigned long)sysconf_address(sc);
- stx7141_wrt_table[_SYS_CFG11_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 4, 0, 0, "pm");
- stx7141_wrt_table[_SYS_STA4] = (unsigned long)sysconf_address(sc);
- stx7141_wrt_table[_SYS_STA4_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 3, 0, 0, "pm");
- stx7141_wrt_table[_SYS_STA3] = (unsigned long)sysconf_address(sc);
- stx7141_wrt_table[_SYS_STA3_MASK] = sysconf_mask(sc);
- stx7141_wrt_table[_SYS_STA3_VALUE] = 0;
- return sh4_suspend_register(&st40data);
-}
-
-late_initcall(suspend_platform_setup);
deleted file mode 100644
@@ -1,261 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/suspend-stx7200.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/irqflags.h>
-#include <linux/stm/sysconf.h>
-#include <linux/stm/pm.h>
-#include <linux/irq.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/pm.h>
-#include <asm/irq-ilc.h>
-
-#include "./soc-stx7200.h"
-
-#define _SYS_STA4 (3)
-#define _SYS_STA4_MASK (4)
-#define _SYS_STA6 (5)
-#define _SYS_STA6_MASK (6)
-
-/* To powerdown the LMIs */
-#define _SYS_CFG38 (7)
-#define _SYS_CFG38_MASK (8)
-#define _SYS_CFG39 (9)
-#define _SYS_CFG39_MASK (10)
-
-/* *************************
- * STANDBY INSTRUCTION TABLE
- * *************************
- */
-#ifdef CONFIG_PM_DEBUG
-static unsigned long stx7200_standby_table[] __cacheline_aligned = {
-/* Down scale the GenA.Pll0 and GenA.Pll2*/
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS),
-CLK_OR_LONG(CLKA_PLL2, CLKA_PLL2_BYPASS),
-
-CLK_OR_LONG(CLKA_PWR_CFG, PWR_CFG_PLL0_OFF | PWR_CFG_PLL2_OFF),
-#if 0
-CLK_AND_LONG(CLKA_PLL0, ~(0x7ffff)),
-CLK_AND_LONG(CLKA_PLL2, ~(0x7ffff)),
-
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_SUSPEND),
-CLK_OR_LONG(CLKA_PLL2, CLKA_PLL2_SUSPEND),
-
-CLK_AND_LONG(CLKA_PWR_CFG, ~(PWR_CFG_PLL0_OFF | PWR_CFG_PLL2_OFF)),
-
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)),
-CLK_AND_LONG(CLKA_PLL2, ~(CLKA_PLL2_BYPASS)),
-#endif
-/* END. */
-_END(),
-
-/* Restore the GenA.Pll0 and GenA.PLL2 original frequencies */
-#if 0
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS),
-CLK_OR_LONG(CLKA_PLL2, CLKA_PLL2_BYPASS),
-
-CLK_OR_LONG(CLKA_PWR_CFG, PWR_CFG_PLL0_OFF | PWR_CFG_PLL2_OFF),
-
-DATA_LOAD(0x0),
-IMMEDIATE_SRC0(CLKA_PLL0_BYPASS),
-_OR(),
-CLK_STORE(CLKA_PLL0),
-
-DATA_LOAD(0x1),
-IMMEDIATE_SRC0(CLKA_PLL2_BYPASS),
-_OR(),
-CLK_STORE(CLKA_PLL2),
-#endif
-CLK_AND_LONG(CLKA_PWR_CFG, ~(PWR_CFG_PLL0_OFF | PWR_CFG_PLL2_OFF)),
-CLK_WHILE_NEQ(CLKA_PLL0, CLKA_PLL0_LOCK, CLKA_PLL0_LOCK),
-CLK_WHILE_NEQ(CLKA_PLL2, CLKA_PLL2_LOCK, CLKA_PLL2_LOCK),
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)),
-CLK_AND_LONG(CLKA_PLL2, ~(CLKA_PLL2_BYPASS)),
-
-_DELAY(),
-/* END. */
-_END()
-};
-#endif
-
-/* *********************
- * MEM INSTRUCTION TABLE
- * *********************
- */
-
-static unsigned long stx7200_mem_table[] __cacheline_aligned = {
-/* 1. Enables the DDR self refresh mode */
-DATA_OR_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-DATA_OR_LONG(_SYS_CFG39, _SYS_CFG39_MASK),
- /* waits until the ack bit is zero */
-DATA_WHILE_NEQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-DATA_WHILE_NEQ(_SYS_STA6, _SYS_STA6_MASK, _SYS_STA6_MASK),
-
- /* waits until the ack bit is zero */
-/* 2. Down scale the GenA.Pll0, GenA.Pll1 and GenA.Pll2*/
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS),
-CLK_OR_LONG(CLKA_PLL1, CLKA_PLL1_BYPASS),
-CLK_OR_LONG(CLKA_PLL2, CLKA_PLL2_BYPASS),
-
-CLK_OR_LONG(CLKA_PWR_CFG, PWR_CFG_PLL0_OFF | PWR_CFG_PLL1_OFF | PWR_CFG_PLL2_OFF),
-#if 0
-CLK_AND_LONG(CLKA_PLL0, ~(0x7ffff)),
-CLK_AND_LONG(CLKA_PLL1, ~(0x7ffff)),
-CLK_AND_LONG(CLKA_PLL2, ~(0x7ffff)),
-
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_SUSPEND),
-CLK_OR_LONG(CLKA_PLL1, CLKA_PLL1_SUSPEND),
-CLK_OR_LONG(CLKA_PLL2, CLKA_PLL2_SUSPEND),
-
-CLK_AND_LONG(CLKA_PWR_CFG, ~(PWR_CFG_PLL0_OFF | PWR_CFG_PLL1_OFF | PWR_CFG_PLL2_OFF)),
-
-CLK_WHILE_NEQ(CLKA_PLL0, CLKA_PLL0_LOCK, CLKA_PLL0_LOCK),
-CLK_WHILE_NEQ(CLKA_PLL1, CLKA_PLL1_LOCK, CLKA_PLL1_LOCK),
-CLK_WHILE_NEQ(CLKA_PLL2, CLKA_PLL2_LOCK, CLKA_PLL2_LOCK),
-
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)),
-CLK_AND_LONG(CLKA_PLL1, ~(CLKA_PLL1_BYPASS)),
-CLK_AND_LONG(CLKA_PLL2, ~(CLKA_PLL2_BYPASS)),
-#endif
-/* END. */
-_END() ,
-
-/* Restore the GenA.Pll0 and GenA.PLL2 original frequencies */
-#if 0
-CLK_OR_LONG(CLKA_PLL0, CLKA_PLL0_BYPASS),
-CLK_OR_LONG(CLKA_PLL1, CLKA_PLL1_BYPASS),
-CLK_OR_LONG(CLKA_PLL2, CLKA_PLL2_BYPASS),
-
-CLK_OR_LONG(CLKA_PWR_CFG, PWR_CFG_PLL0_OFF | PWR_CFG_PLL1_OFF | PWR_CFG_PLL2_OFF),
-
-DATA_LOAD(0x0),
-IMMEDIATE_SRC0(CLKA_PLL0_BYPASS),
-_OR(),
-CLK_STORE(CLKA_PLL0),
-
-DATA_LOAD(0x1),
-IMMEDIATE_SRC0(CLKA_PLL1_BYPASS),
-_OR(),
-CLK_STORE(CLKA_PLL1),
-
-DATA_LOAD(0x2),
-IMMEDIATE_SRC0(CLKA_PLL2_BYPASS),
-_OR(),
-CLK_STORE(CLKA_PLL2),
-#endif
-CLK_AND_LONG(CLKA_PWR_CFG, ~(PWR_CFG_PLL0_OFF | PWR_CFG_PLL1_OFF | PWR_CFG_PLL2_OFF)),
-/* Wait PLLs lock */
-CLK_WHILE_NEQ(CLKA_PLL0, CLKA_PLL0_LOCK, CLKA_PLL0_LOCK),
-CLK_WHILE_NEQ(CLKA_PLL1, CLKA_PLL1_LOCK, CLKA_PLL1_LOCK),
-CLK_WHILE_NEQ(CLKA_PLL2, CLKA_PLL2_LOCK, CLKA_PLL2_LOCK),
-
-CLK_AND_LONG(CLKA_PLL0, ~(CLKA_PLL0_BYPASS)),
-CLK_AND_LONG(CLKA_PLL1, ~(CLKA_PLL1_BYPASS)),
-CLK_AND_LONG(CLKA_PLL2, ~(CLKA_PLL2_BYPASS)),
-
-DATA_AND_NOT_LONG(_SYS_CFG38, _SYS_CFG38_MASK),
-DATA_AND_NOT_LONG(_SYS_CFG39, _SYS_CFG39_MASK),
-DATA_WHILE_EQ(_SYS_STA4, _SYS_STA4_MASK, _SYS_STA4_MASK),
-
-/* wait until the ack bit is high */
-DATA_WHILE_EQ(_SYS_STA6, _SYS_STA6_MASK, _SYS_STA6_MASK),
-
-_DELAY(),
-_DELAY(),
-_DELAY(),
-/* END. */
-_END()
-};
-
-static unsigned long stx7200_wrt_table[16] __cacheline_aligned;
-
-static int stx7200_suspend_prepare(suspend_state_t state)
-{
-#ifdef CONFIG_PM_DEBUG
- if (state == PM_SUSPEND_STANDBY) {
- stx7200_wrt_table[0] =
- readl(CLOCKGEN_BASE_ADDR + CLKA_PLL0) & 0x7ffff;
- stx7200_wrt_table[1] =
- readl(CLOCKGEN_BASE_ADDR + CLKA_PLL2) & 0x7ffff;
- } else
-#endif
- {
- stx7200_wrt_table[0] =
- readl(CLOCKGEN_BASE_ADDR + CLKA_PLL0) & 0x7ffff;
- stx7200_wrt_table[1] =
- readl(CLOCKGEN_BASE_ADDR + CLKA_PLL1) & 0x7ffff;
- stx7200_wrt_table[2] =
- readl(CLOCKGEN_BASE_ADDR + CLKA_PLL2) & 0x7ffff;
- }
- return 0;
-}
-
-
-static unsigned long stx7200_iomem[2] __cacheline_aligned = {
- stx7200_wrt_table, /* To access Sysconf */
- CLOCKGEN_BASE_ADDR}; /* Clockgen A */
-
-static int stx7200_evttoirq(unsigned long evt)
-{
- return ((evt < 0x400) ? ilc2irq(evt) : evt2irq(evt));
-}
-
-static struct sh4_suspend_t st40data __cacheline_aligned = {
- .iobase = stx7200_iomem,
- .ops.prepare = stx7200_suspend_prepare,
- .evt_to_irq = stx7200_evttoirq,
-#ifdef CONFIG_PM_DEBUG
- .stby_tbl = (unsigned long)stx7200_standby_table,
- .stby_size = DIV_ROUND_UP(ARRAY_SIZE(stx7200_standby_table) *
- sizeof(long), L1_CACHE_BYTES),
-#endif
- .mem_tbl = (unsigned long)stx7200_mem_table,
- .mem_size = DIV_ROUND_UP(ARRAY_SIZE(stx7200_mem_table) * sizeof(long),
- L1_CACHE_BYTES),
- .wrt_tbl = (unsigned long)stx7200_wrt_table,
- .wrt_size = DIV_ROUND_UP(ARRAY_SIZE(stx7200_wrt_table) * sizeof(long),
- L1_CACHE_BYTES),
-};
-
-static int __init suspend_platform_setup()
-{
- struct sysconf_field* sc;
-
- sc = sysconf_claim(SYS_STA, 4, 0, 0, "pm");
- stx7200_wrt_table[_SYS_STA4] = (unsigned long)sysconf_address(sc);
- stx7200_wrt_table[_SYS_STA4_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_STA, 6, 0, 0, "pm");
- stx7200_wrt_table[_SYS_STA6] = (unsigned long)sysconf_address(sc);
- stx7200_wrt_table[_SYS_STA6_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_CFG, 38, 20, 20, "pm");
- stx7200_wrt_table[_SYS_CFG38] = (unsigned long)sysconf_address(sc);
- stx7200_wrt_table[_SYS_CFG38_MASK] = sysconf_mask(sc);
-
- sc = sysconf_claim(SYS_CFG, 39, 20, 20, "pm");
- stx7200_wrt_table[_SYS_CFG39] = (unsigned long)sysconf_address(sc);
- stx7200_wrt_table[_SYS_CFG39_MASK] = sysconf_mask(sc);
-
-#ifdef CONFIG_PM_DEBUG
- ctrl_outl(0xc, CKGA_CLKOUT_SEL +
- CLOCKGEN_BASE_ADDR); /* sh4:2 routed on SYSCLK_OUT */
-#endif
- return sh4_suspend_register(&st40data);
-}
-
-late_initcall(suspend_platform_setup);
deleted file mode 100644
@@ -1,128 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/suspend-st40.c
- * -------------------------------------------------------------------------
- * Copyright (C) 2008 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * ------------------------------------------------------------------------- */
-
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/irqflags.h>
-#include <linux/kobject.h>
-#include <linux/stat.h>
-#include <linux/clk.h>
-#include <linux/hardirq.h>
-#include <linux/jiffies.h>
-#include <asm/system.h>
-#include <asm/cpu/cacheflush.h>
-#include <asm/io.h>
-#include <asm-generic/bug.h>
-#include <asm/pm.h>
-
-#undef dbg_print
-
-#ifdef CONFIG_PM_DEBUG
-#define dbg_print(fmt, args...) \
- printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
-#else
-#define dbg_print(fmt, args...)
-#endif
-
-extern struct kset power_subsys;
-
-unsigned int wokenup_by ;
-
-unsigned long sh4_suspend(struct sh4_suspend_t *pdata,
- unsigned long instr_tbl, unsigned long instr_tbl_end);
-
-static inline unsigned long _10_ms_lpj(void)
-{
- static struct clk *sh4_clk;
- if (!sh4_clk)
- sh4_clk = clk_get(NULL, "sh4_clk");
- return clk_get_rate(sh4_clk) / (100 * 2);
-}
-
-static struct sh4_suspend_t *data;
-static int sh4_suspend_enter(suspend_state_t state)
-{
- unsigned long flags;
- unsigned long instr_tbl, instr_tbl_end;
-
- data->l_p_j = _10_ms_lpj();
-
- /* Must wait for serial buffers to clear */
- mdelay(500);
-
- local_irq_save(flags);
-
- /* sets the right instruction table */
- if (state == PM_SUSPEND_STANDBY) {
- instr_tbl = data->stby_tbl;
- instr_tbl_end = data->stby_size;
- } else {
- instr_tbl = data->mem_tbl;
- instr_tbl_end = data->mem_size;
- }
-
- BUG_ON(in_irq());
-
- wokenup_by = sh4_suspend(data, instr_tbl, instr_tbl_end);
-
-/*
- * without the evt_to_irq function the INTEVT is returned
- */
- if (data->evt_to_irq)
- wokenup_by = data->evt_to_irq(wokenup_by);
-
- BUG_ON(in_irq());
-
- local_irq_restore(flags);
-
- printk(KERN_INFO "sh4 woken up by: 0x%x\n", wokenup_by);
-
- return 0;
-}
-
-static ssize_t power_wokenupby_show(struct kset *subsys, char *buf)
-{
- return sprintf(buf, "%d\n", wokenup_by);
-}
-
-static struct subsys_attribute wokenup_by_attr =
-__ATTR(wokenup-by, S_IRUGO, power_wokenupby_show, NULL);
-
-static int sh4_suspend_valid_both(suspend_state_t state)
-{
- return 1;
-}
-
-int __init sh4_suspend_register(struct sh4_suspend_t *pdata)
-{
- int dummy;
-
- if (!pdata)
- return -EINVAL;
- data = pdata;
- data->ops.enter = sh4_suspend_enter;
- if (data->stby_tbl && data->stby_size)
- data->ops.valid = sh4_suspend_valid_both;
- else
- data->ops.valid = pm_valid_only_mem;
-
- pm_set_ops(&data->ops);
-
- dummy = subsys_create_file(&power_subsys, &wokenup_by_attr);
-
- printk(KERN_INFO "sh4 suspend support registered\n");
-
- return 0;
-}
deleted file mode 100644
@@ -1,169 +0,0 @@
-/*
- * -------------------------------------------------------------------------
- * <linux_root>/arch/sh/kernel/cpu/sh4/swsusp.S
- * -------------------------------------------------------------------------
- * Copyright (C) 2009 STMicroelectronics
- * Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
- *
- * May be copied or modified under the terms of the GNU General Public
- * License V.2 ONLY. See linux/COPYING for more information.
- *
- * This may not use any stack, nor any variable that is not "NoSave"
- * ------------------------------------------------------------------------- */
-
-#include <linux/linkage.h>
-
-#define OFF_R8 ( 0 )
-#define OFF_R9 (4 + OFF_R8 )
-#define OFF_R10 (4 + OFF_R9 )
-#define OFF_R11 (4 + OFF_R10 )
-#define OFF_R12 (4 + OFF_R11 )
-#define OFF_R13 (4 + OFF_R12 )
-#define OFF_R14 (4 + OFF_R13 )
-#define OFF_R15 (4 + OFF_R14 )
-#define OFF_PR (4 + OFF_R15 )
-#define OFF_SR (4 + OFF_PR )
-#define OFF_R6_BK (4 + OFF_SR )
-#define OFF_R7_BK (4 + OFF_R6_BK )
-
-.text ;
-.balign 32 ; ! to be icache aligned
-
-ENTRY(swsusp_arch_suspend) ;
-/*
- * Here I have to save all the registers
- */
- mov.l 1f, r0
- mov.l r8, @(OFF_R8, r0)
- mov.l r9, @(OFF_R9, r0)
- mov.l r10, @(OFF_R10, r0)
- mov.l r11, @(OFF_R11, r0)
- mov.l r12, @(OFF_R12, r0)
- mov.l r13, @(OFF_R13, r0)
- mov.l r14, @(OFF_R14, r0)
- mov.l r15, @(OFF_R15, r0)
- stc r6_bank, r1
- mov.l r1, @(OFF_R6_BK, r0)
- stc r7_bank, r1
- mov.l r1, @(OFF_R7_BK, r0)
-
- sts pr, r1
- mov.l r1, @(OFF_PR, r0)
- stc sr, r1
- mov.l r1, @(OFF_SR, r0)
-
-! Now call the swsusp_save
- mov.l 2f, r0
- jsr @r0
- nop
- ! Now in r0 there is the returned value of swsusp_save
- mov.l 1f, r4
- ! Reload the right pr
- mov.l @(OFF_PR, r4), r1
- lds r1, pr
- rts
- nop
-
-.balign 4;
-1:.long saved_context_reg;
-2:.long swsusp_save;
-
-#define JUMPER() bra 201f; \
- nop; \
- 200: bra 200f; \
- nop; ; \
- 201:
-
-.balign 32 ; ! icache aligned
-ENTRY(swsusp_arch_resume)
- bra 200f ! start the jump sequence
- nop
-really_swsusp_arch_resume:
- mov.l 10f, r6 ! load the restore_pblist
- mov.l @r6, r6
-0: tst r6, r6 ! check if there are other 'pages'(pbe)
- bt/s 20f
- mov #64, r7 ! r7 = 64
- shll r7 ! r7 = 128 dcache line(128 * 32) = 4096...
-
- JUMPER()
-
- mov.l @(0, r6), r5 ! the source address
- mov.l @(4, r6), r4 ! the destination address
- mov.l @(8, r6), r6 ! the next pbe address
- mov r5, r3
- add #32, r3 ! the next icache line source address
-1:
- mov.l @r5+, r0 ! 1.
- pref @r3 ! prefect the next icache line
- movca.l r0, @r4
- mov.l @r5+, r0 ! 2.
- mov.l r0, @(4, r4)
- mov.l @r5+, r0 ! 3.
- JUMPER()
-
- mov.l r0, @(8, r4)
- mov.l @r5+, r0 ! 4.
- mov.l r0, @(12, r4)
- mov.l @r5+, r0 ! 5.
- mov.l r0, @(16, r4)
- mov.l @r5+, r0 ! 6
- mov.l r0, @(20, r4)
-
- JUMPER()
-
- mov.l @r5 +, r0 ! 7
- mov.l r0, @(24, r4)
- mov.l @r5+, r0 ! 8
- mov.l r0, @(28, r4)
- ocbp @r4
- add #32, r4
- add #32, r3
- dt r7
- bf 1b ! check if the page is complete
-
- JUMPER()
-
- bra 0b
- nop
-
- 20:
-
- !now restore the previous value...
- mov.l 11f, r0
- mov.l @(OFF_R8, r0), r8
- mov.l @(OFF_R9, r0), r9
- mov.l @(OFF_R10, r0), r10
-
- JUMPER()
-
- mov.l @(OFF_R11, r0), r11
- mov.l @(OFF_R12, r0), r12
- mov.l @(OFF_R13, r0), r13
- mov.l @(OFF_R14, r0), r14
- mov.l @(OFF_R15, r0), r15
- mov.l @(OFF_R6_BK, r0), r1
- ldc r1, r6_bank
- mov.l @(OFF_R7_BK, r0), r1
- ldc r1, r7_bank
-
- JUMPER()
-
- mov.l 12f, r1
- jsr @r1
- nop
- mov.l 11f, r0
- mov.l @(OFF_PR, r0), r1
- lds r1, pr
- mov.l @(OFF_SR, r0), r1
- ldc r1, sr
- rts
- mov #0, r0
-
-200: bra really_swsusp_arch_resume
- nop
-
-.balign 4 ;
-10:.long restore_pblist ;
-11:.long saved_context_reg ;
-12:.long flush_cache_all ;