From patchwork Tue Oct 19 01:43:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 264051 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o9J1hocA018189 for ; Tue, 19 Oct 2010 01:43:50 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754294Ab0JSBnr (ORCPT ); Mon, 18 Oct 2010 21:43:47 -0400 Received: from mail-pz0-f46.google.com ([209.85.210.46]:60640 "EHLO mail-pz0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753666Ab0JSBnq (ORCPT ); Mon, 18 Oct 2010 21:43:46 -0400 Received: by pzk3 with SMTP id 3so155300pzk.19 for ; Mon, 18 Oct 2010 18:43:46 -0700 (PDT) Received: by 10.142.164.7 with SMTP id m7mr4111261wfe.105.1287452626176; Mon, 18 Oct 2010 18:43:46 -0700 (PDT) Received: from localhost.localdomain (49.14.32.202.bf.2iij.net [202.32.14.49]) by mx.google.com with ESMTPS id e14sm17644525wfg.20.2010.10.18.18.43.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 18 Oct 2010 18:43:45 -0700 (PDT) From: Nobuhiro Iwamatsu To: linux-sh@vger.kernel.org Cc: lethal@linux-sh.org, Nobuhiro Iwamatsu Subject: [RFC/PATCH] sh: Add 32bit cou mode to cpu_flags Date: Tue, 19 Oct 2010 10:43:29 +0900 Message-Id: <1287452609-14530-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Mailer: git-send-email 1.7.1 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 19 Oct 2010 01:43:50 +0000 (UTC) diff --git a/arch/sh/include/asm/cpu-features.h b/arch/sh/include/asm/cpu-features.h index 694abe4..dc1265b 100644 --- a/arch/sh/include/asm/cpu-features.h +++ b/arch/sh/include/asm/cpu-features.h @@ -22,5 +22,6 @@ #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ +#define CPU_IS_32BIT_MODE 0x0400 /* linux kernel works 32bit mode */ #endif /* __ASM_SH_CPU_FEATURES_H */ diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index b93458f..4bda234 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -189,6 +189,10 @@ void __cpuinit cpu_probe(void) break; } +#ifdef CONFIG_32BIT + boot_cpu_data.flags |= CPU_IS_32BIT_MODE; +#endif + /* * On anything that's not a direct-mapped cache, look to the CVR * for I/D-cache specifics. diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 4e27846..460ac72 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -352,7 +352,8 @@ EXPORT_SYMBOL(get_cpu_subtype); /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */ static const char *cpu_flags[] = { "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr", - "ptea", "llsc", "l2", "op32", "pteaex", NULL + "ptea", "llsc", "l2", "op32", "pteaex", "32bit", + NULL }; static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c) @@ -410,6 +411,11 @@ static int show_cpuinfo(struct seq_file *m, void *v) else seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor); + if (c->flags & CPU_IS_32BIT_MODE) + seq_printf(m, "cpu mode\t: 32bit\n"); + else + seq_printf(m, "cpu mode\t: 29bit\n"); + show_cpuflags(m, c); seq_printf(m, "cache type\t: ");