From patchwork Fri Feb 8 15:02:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 2116601 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id E75573FD56 for ; Fri, 8 Feb 2013 15:08:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1946164Ab3BHPIU (ORCPT ); Fri, 8 Feb 2013 10:08:20 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:34191 "EHLO relmlor2.renesas.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1945976Ab3BHPIT (ORCPT ); Fri, 8 Feb 2013 10:08:19 -0500 X-Greylist: delayed 300 seconds by postgrey-1.27 at vger.kernel.org; Fri, 08 Feb 2013 10:08:19 EST Received: from relmlir1.idc.renesas.com ([10.200.68.151]) by relmlor2.idc.renesas.com ( SJSMS) with ESMTP id <0MHW005XMPTHUA40@relmlor2.idc.renesas.com> for linux-sh@vger.kernel.org; Sat, 09 Feb 2013 00:03:17 +0900 (JST) Received: from relmlac1.idc.renesas.com ([10.200.69.21]) by relmlir1.idc.renesas.com (SJSMS) with ESMTP id <0MHW00COCPTHXR30@relmlir1.idc.renesas.com> for linux-sh@vger.kernel.org; Sat, 09 Feb 2013 00:03:17 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id CB91380193; Sat, 09 Feb 2013 00:03:17 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id C66A180177; Sat, 09 Feb 2013 00:03:17 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac1.idc.renesas.com with ESMTP id AAG22703; Sat, 09 Feb 2013 00:03:17 +0900 X-IronPort-AV: E=Sophos; i="4.84,629,1355065200"; d="scan'208"; a="116561811" Received: from unknown (HELO relay41.aps.necel.com) ([10.29.19.9]) by relmlii2.idc.renesas.com with ESMTP; Sat, 09 Feb 2013 00:03:17 +0900 Received: from julia (du2com5.eu.necel.com [172.29.24.35] (may be forged)) by relay41.aps.necel.com (8.14.4+Sun/8.14.4) with ESMTP id r18F3ETC002217; Sat, 09 Feb 2013 00:03:14 +0900 (JST) Received: by julia (Postfix, from userid 2) id 68D2D4E90D; Fri, 08 Feb 2013 16:03:15 +0100 (CET) Received: from du0smtp.eu.necel.com (unknown [172.29.24.86]) by julia (Postfix) with ESMTP id 4171B4E901; Fri, 08 Feb 2013 16:03:15 +0100 (CET) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by du0smtp.eu.necel.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2013020816030643-17930 ; Fri, 08 Feb 2013 16:03:06 +0100 From: Phil Edworthy To: Paul Mundt Cc: linux-sh@vger.kernel.org, Laurent Pinchart , Phil Edworthy Subject: [PATCH RFC] sh: pfc: Add ability to use separate read & write GPIO data regs X-Mailer: git-send-email 1.7.5.4 X-TNEFEvaluated: 1 Message-id: <1360335771-4468-1-git-send-email-phil.edworthy@renesas.com> Date: Fri, 08 Feb 2013 15:02:51 +0000 X-MIMETrack: Itemize by SMTP Server on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 08.02.2013 16:03:06, Serialize by Router on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 08.02.2013 16:03:13, Serialize complete at 08.02.2013 16:03:13 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org On several devices, there are separate registers for data input and data output. Signed-off-by: Phil Edworthy --- drivers/sh/pfc/core.c | 5 +++-- include/linux/sh_pfc.h | 8 +++++++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/sh/pfc/core.c b/drivers/sh/pfc/core.c index 6816937..173126e 100644 --- a/drivers/sh/pfc/core.c +++ b/drivers/sh/pfc/core.c @@ -163,14 +163,14 @@ void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " "r_width = %ld\n", - dr->reg, !!value, pos, dr->reg_width); + dr->wreg, !!value, pos, dr->reg_width); if (value) set_bit(pos, &dr->reg_shadow); else clear_bit(pos, &dr->reg_shadow); - gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); + gpio_write_raw_reg(dr->mapped_wreg, dr->reg_width, dr->reg_shadow); } EXPORT_SYMBOL_GPL(sh_pfc_write_bit); @@ -256,6 +256,7 @@ static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio) break; data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg); + data_reg->mapped_wreg = pfc_phys_to_virt(pfc, data_reg->wreg); for (n = 0; n < data_reg->reg_width; n++) { if (data_reg->enum_ids[n] == gpiop->enum_id) { diff --git a/include/linux/sh_pfc.h b/include/linux/sh_pfc.h index c19a092..bbf955b 100644 --- a/include/linux/sh_pfc.h +++ b/include/linux/sh_pfc.h @@ -68,10 +68,16 @@ struct pinmux_data_reg { unsigned long reg, reg_width, reg_shadow; pinmux_enum_t *enum_ids; void __iomem *mapped_reg; + unsigned long wreg; /* separate write reg */ + void __iomem *mapped_wreg; }; #define PINMUX_DATA_REG(name, r, r_width) \ - .reg = r, .reg_width = r_width, \ + .reg = r, .wreg = r, .reg_width = r_width, \ + .enum_ids = (pinmux_enum_t [r_width]) \ + +#define PINMUX_DATA_REG2(name, r, r2, r_width) \ + .reg = r, .wreg = r2, .reg_width = r_width, \ .enum_ids = (pinmux_enum_t [r_width]) \ struct pinmux_irq {