From patchwork Mon Mar 18 16:38:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 2294431 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 968553FD8C for ; Mon, 18 Mar 2013 16:39:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752766Ab3CRQj1 (ORCPT ); Mon, 18 Mar 2013 12:39:27 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:58367 "EHLO relmlor3.renesas.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753723Ab3CRQjX (ORCPT ); Mon, 18 Mar 2013 12:39:23 -0400 Received: from relmlir3.idc.renesas.com ([10.200.68.153]) by relmlor3.idc.renesas.com ( SJSMS) with ESMTP id <0MJV00HDX7LMPPD0@relmlor3.idc.renesas.com> for linux-sh@vger.kernel.org; Tue, 19 Mar 2013 01:39:22 +0900 (JST) Received: from relmlac4.idc.renesas.com ([10.200.69.24]) by relmlir3.idc.renesas.com ( SJSMS) with ESMTP id <0MJV00D3K7LMTE00@relmlir3.idc.renesas.com> for linux-sh@vger.kernel.org; Tue, 19 Mar 2013 01:39:22 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 437A0480A4; Tue, 19 Mar 2013 01:39:22 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 3E6CC480A0; Tue, 19 Mar 2013 01:39:22 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac4.idc.renesas.com with ESMTP id BAB28578; Tue, 19 Mar 2013 01:39:22 +0900 X-IronPort-AV: E=Sophos; i="4.84,865,1355065200"; d="scan'208"; a="120861159" Received: from unknown (HELO relay61.aps.necel.com) ([10.29.19.64]) by relmlii1.idc.renesas.com with ESMTP; Tue, 19 Mar 2013 01:39:22 +0900 Received: from julia (du2com5.eu.necel.com [172.29.24.35] (may be forged)) by relay61.aps.necel.com (8.14.4+Sun/8.14.4) with ESMTP id r2IGdIAq000631; Tue, 19 Mar 2013 01:39:18 +0900 (JST) Received: by julia (Postfix, from userid 2) id D25D7800E; Mon, 18 Mar 2013 17:39:17 +0100 (CET) Received: from du0smtp.eu.necel.com (unknown [172.29.24.86]) by julia (Postfix) with ESMTP id C5F04800D; Mon, 18 Mar 2013 17:39:17 +0100 (CET) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by du0smtp.eu.necel.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2013031817391690-409608 ; Mon, 18 Mar 2013 17:39:16 +0100 From: Phil Edworthy To: linux-sh@vger.kernel.org Cc: Simon , Magnus , Phil Edworthy Subject: [PATCH] ARM: shmobile: r8a7779: Add PCIe clock support X-Mailer: git-send-email 1.7.5.4 X-TNEFEvaluated: 1 Message-id: <1363624732-24660-1-git-send-email-phil.edworthy@renesas.com> Date: Mon, 18 Mar 2013 16:38:52 +0000 X-MIMETrack: Itemize by SMTP Server on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 18.03.2013 17:39:17, Serialize by Router on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 18.03.2013 17:39:17, Serialize complete at 18.03.2013 17:39:17 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Signed-off-by: Phil Edworthy --- Depends on "r8a7779: Add Display Unit clock support" arch/arm/mach-shmobile/clock-r8a7779.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 9ea6087..a017418 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = { }; enum { MSTP323, MSTP322, MSTP321, MSTP320, + MSTP116, MSTP103, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -99,6 +100,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 16, 0), /* PCIe */ [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ @@ -182,6 +184,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ + CLKDEV_DEV_ID("rcar-pcie.0", &mstp_clks[MSTP116]), /* PCIe */ }; void __init r8a7779_clock_init(void)