diff mbox

[v2] ARM: shmobile: r8a7779: Add PCIe clocks

Message ID 1363685757-8159-1-git-send-email-phil.edworthy@renesas.com (mailing list archive)
State Superseded
Headers show

Commit Message

Phil Edworthy March 19, 2013, 9:35 a.m. UTC
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
v2:
  Rebased on renesas soc branch.
  Removed ".0" from clock name.

 arch/arm/mach-shmobile/clock-r8a7779.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

Comments

Simon Horman March 21, 2013, 10:33 a.m. UTC | #1
On Tue, Mar 19, 2013 at 09:35:57AM +0000, Phil Edworthy wrote:
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> ---
> v2:
>   Rebased on renesas soc branch.
>   Removed ".0" from clock name.

Thanks Phil, applied to the soc branch.
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Simon Horman April 9, 2013, 1:31 p.m. UTC | #2
On Thu, Mar 21, 2013 at 07:33:37PM +0900, Simon Horman wrote:
> On Tue, Mar 19, 2013 at 09:35:57AM +0000, Phil Edworthy wrote:
> > 
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > ---
> > v2:
> >   Rebased on renesas soc branch.
> >   Removed ".0" from clock name.
> 
> Thanks Phil, applied to the soc branch.

I'm terribly sorry about this but it appears that I didn't apply it after
all. Could you rebase it on the next branch of my tree and repost?
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diff mbox

Patch

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index d9edeaf..a23c5eb 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,7 +87,7 @@  static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-	MSTP115,
+	MSTP116, MSTP115,
 	MSTP103, MSTP101, MSTP100,
 	MSTP030,
 	MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -100,6 +100,7 @@  static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
 	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+	[MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 16, 0), /* PCIe */
 	[MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */
 	[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1,  3, 0), /* DU */
 	[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
@@ -159,6 +160,7 @@  static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("peripheral_clk",	&div4_clks[DIV4_P]),
 
 	/* MSTP32 clocks */
+	CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
 	CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
 	CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
 	CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */