From patchwork Tue Mar 19 09:35:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 2299691 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 50557DFB79 for ; Tue, 19 Mar 2013 09:39:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755376Ab3CSJja (ORCPT ); Tue, 19 Mar 2013 05:39:30 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:57039 "EHLO relmlor1.renesas.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754463Ab3CSJj3 (ORCPT ); Tue, 19 Mar 2013 05:39:29 -0400 Received: from relmlir2.idc.renesas.com ([10.200.68.152]) by relmlor1.idc.renesas.com ( SJSMS) with ESMTP id <0MJW00G0FION4OA0@relmlor1.idc.renesas.com> for linux-sh@vger.kernel.org; Tue, 19 Mar 2013 18:36:23 +0900 (JST) Received: from relmlac4.idc.renesas.com ([10.200.69.24]) by relmlir2.idc.renesas.com ( SJSMS) with ESMTP id <0MJW004OQIONM100@relmlir2.idc.renesas.com> for linux-sh@vger.kernel.org; Tue, 19 Mar 2013 18:36:23 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 8B898480A5; Tue, 19 Mar 2013 18:36:23 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 865D3480A0; Tue, 19 Mar 2013 18:36:23 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac4.idc.renesas.com with ESMTP id UAM03577; Tue, 19 Mar 2013 18:36:23 +0900 X-IronPort-AV: E=Sophos; i="4.84,870,1355065200"; d="scan'208"; a="121136357" Received: from unknown (HELO relay41.aps.necel.com) ([10.29.19.9]) by relmlii2.idc.renesas.com with ESMTP; Tue, 19 Mar 2013 18:36:23 +0900 Received: from julia (du2com5.eu.necel.com [172.29.24.35] (may be forged)) by relay41.aps.necel.com (8.14.4+Sun/8.14.4) with ESMTP id r2J9aMGs026594; Tue, 19 Mar 2013 18:36:22 +0900 (JST) Received: by julia (Postfix, from userid 2) id BE2C44EA6D; Tue, 19 Mar 2013 10:36:21 +0100 (CET) Received: from du0smtp.eu.necel.com (unknown [172.29.24.86]) by julia (Postfix) with ESMTP id B253C4EA67; Tue, 19 Mar 2013 10:36:21 +0100 (CET) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by du0smtp.eu.necel.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2013031910362087-420363 ; Tue, 19 Mar 2013 10:36:20 +0100 From: Phil Edworthy To: linux-sh@vger.kernel.org Cc: Simon , Magnus , Sergei Shtylyov , Phil Edworthy Subject: [PATCH v2] ARM: shmobile: r8a7779: Add PCIe clocks X-Mailer: git-send-email 1.7.5.4 In-reply-to: <51474DB0.2010705@cogentembedded.com> References: <51474DB0.2010705@cogentembedded.com> X-TNEFEvaluated: 1 Message-id: <1363685757-8159-1-git-send-email-phil.edworthy@renesas.com> Date: Tue, 19 Mar 2013 09:35:57 +0000 X-MIMETrack: Itemize by SMTP Server on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 19.03.2013 10:36:21, Serialize by Router on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 19.03.2013 10:36:21, Serialize complete at 19.03.2013 10:36:21 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Signed-off-by: Phil Edworthy --- v2: Rebased on renesas soc branch. Removed ".0" from clock name. arch/arm/mach-shmobile/clock-r8a7779.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index d9edeaf..a23c5eb 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -87,7 +87,7 @@ static struct clk div4_clks[DIV4_NR] = { }; enum { MSTP323, MSTP322, MSTP321, MSTP320, - MSTP115, + MSTP116, MSTP115, MSTP103, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -100,6 +100,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 16, 0), /* PCIe */ [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ @@ -159,6 +160,7 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), /* MSTP32 clocks */ + CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */