From patchwork Wed Jul 17 11:00:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 2828526 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 50E619F9CA for ; Wed, 17 Jul 2013 11:01:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0251220174 for ; Wed, 17 Jul 2013 11:01:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6498E20170 for ; Wed, 17 Jul 2013 11:01:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753490Ab3GQLBA (ORCPT ); Wed, 17 Jul 2013 07:01:00 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:59852 "EHLO relmlor3.renesas.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753245Ab3GQLA7 (ORCPT ); Wed, 17 Jul 2013 07:00:59 -0400 Received: from relmlir3.idc.renesas.com ([10.200.68.153]) by relmlor3.idc.renesas.com ( SJSMS) with ESMTP id <0MQ20069RULL3Y60@relmlor3.idc.renesas.com>; Wed, 17 Jul 2013 20:00:57 +0900 (JST) Received: from relmlac4.idc.renesas.com ([10.200.69.24]) by relmlir3.idc.renesas.com ( SJSMS) with ESMTP id <0MQ200J8OULL1G00@relmlir3.idc.renesas.com>; Wed, 17 Jul 2013 20:00:57 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id 3AAAE480A7; Wed, 17 Jul 2013 20:00:57 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id 36B11480A6; Wed, 17 Jul 2013 20:00:57 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac4.idc.renesas.com with ESMTP id WAS24045; Wed, 17 Jul 2013 20:00:57 +0900 X-IronPort-AV: E=Sophos; i="4.89,683,1367938800"; d="scan'208"; a="134343870" Received: from unknown (HELO relay41.aps.necel.com) ([10.29.19.9]) by relmlii2.idc.renesas.com with ESMTP; Wed, 17 Jul 2013 20:00:57 +0900 Received: from julia (du2com5.eu.necel.com [172.29.24.35] (may be forged)) by relay41.aps.necel.com (8.14.4+Sun/8.14.4) with ESMTP id r6HB0tCh004078; Wed, 17 Jul 2013 20:00:55 +0900 (JST) Received: by julia (Postfix, from userid 2) id EB3B98062; Wed, 17 Jul 2013 13:00:54 +0200 (CEST) Received: from du0smtp.eu.necel.com (unknown [172.29.24.86]) by julia (Postfix) with ESMTP id DBEDF8061; Wed, 17 Jul 2013 13:00:54 +0200 (CEST) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by du0smtp.eu.necel.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2013071713005410-275968 ; Wed, 17 Jul 2013 13:00:54 +0200 From: Phil Edworthy To: linux-gpio@vger.kernel.org Cc: linux-sh@vger.kernel.org, Linus Walleij , Laurent Pinchart , Kuninori Morimoto , Phil Edworthy X-Mailer: git-send-email 1.7.9.5 X-TNEFEvaluated: 1 Message-id: <1374058848-6823-1-git-send-email-phil.edworthy@renesas.com> Date: Wed, 17 Jul 2013 12:00:48 +0100 Subject: [PATCH] sh-pfc: r8a7779: Add i2c pin groups X-MIMETrack: Itemize by SMTP Server on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 17.07.2013 13:00:54, Serialize by Router on DU0SMTP/EE/NECEE(Release 8.5.3 HF466|March 09, 2012) at 17.07.2013 13:00:54, Serialize complete at 17.07.2013 13:00:54 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add all I2C pin groups to R8A7779 PFC driver. Signed-off-by: Phil Edworthy Acked-by: Laurent Pinchart --- drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 105 ++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 8e22ca6..777795b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1731,6 +1731,79 @@ static const unsigned int hspi2_b_pins[] = { static const unsigned int hspi2_b_mux[] = { HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, }; +/* - I2C1 ------------------------------------------------------------------ */ +static const unsigned int i2c1_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), +}; +static const unsigned int i2c1_mux[] = { + SCL1_MARK, SDA1_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), +}; +static const unsigned int i2c1_b_mux[] = { + SCL1_B_MARK, SDA1_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; +static const unsigned int i2c1_c_mux[] = { + SCL1_C_MARK, SDA1_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), +}; +static const unsigned int i2c1_d_mux[] = { + SCL1_D_MARK, SDA1_D_MARK, +}; +/* - I2C2 ------------------------------------------------------------------ */ +static const unsigned int i2c2_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), +}; +static const unsigned int i2c2_mux[] = { + SCL2_MARK, SDA2_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30), +}; +static const unsigned int i2c2_c_mux[] = { + SCL2_C_MARK, SDA2_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), +}; +static const unsigned int i2c2_d_mux[] = { + SCL2_D_MARK, SDA2_D_MARK, +}; +/* - I2C3 ------------------------------------------------------------------ */ +static const unsigned int i2c3_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30), +}; +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA, */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30), +}; +static const unsigned int i2c3_b_mux[] = { + SCL3_B_MARK, SDA3_B_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2600,6 +2673,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hspi1_d), SH_PFC_PIN_GROUP(hspi2), SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq0_b), SH_PFC_PIN_GROUP(intc_irq1), @@ -2760,6 +2843,25 @@ static const char * const hspi2_groups[] = { "hspi2_b", }; +static const char * const i2c1_groups[] = { + "i2c1", + "i2c1_b", + "i2c1_c", + "i2c1_d", +}; + +static const char * const i2c2_groups[] = { + "i2c2", + "i2c2_b", + "i2c2_c", + "i2c2_d", +}; + +static const char * const i2c3_groups[] = { + "i2c3", + "i2c3_b", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq0_b", @@ -2943,6 +3045,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hspi0), SH_PFC_FUNCTION(hspi1), SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(mmc0),