From patchwork Tue Oct 1 18:30:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentine Barshak X-Patchwork-Id: 2971361 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DB35C9F245 for ; Tue, 1 Oct 2013 18:31:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8AC2B201B4 for ; Tue, 1 Oct 2013 18:31:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 40A712018C for ; Tue, 1 Oct 2013 18:31:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751540Ab3JASbE (ORCPT ); Tue, 1 Oct 2013 14:31:04 -0400 Received: from mail-la0-f53.google.com ([209.85.215.53]:64621 "EHLO mail-la0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751515Ab3JASbD (ORCPT ); Tue, 1 Oct 2013 14:31:03 -0400 Received: by mail-la0-f53.google.com with SMTP id el20so6273837lab.12 for ; Tue, 01 Oct 2013 11:31:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BBaKm4DHPjPtbfODolSFLAge8MInjOXTviQHyUS4GZc=; b=D+HI2qmQs1F08GEWEpUFNf+duDcczkAH8TjuYQxmHaqRMno9Wjx5tS1zWnZiu00ULx BbCFM57gso4daNcvaNSdZnVtszXyFG2x5YoJv0FDc8L1dYRDO+glAuI7Zm7FPnRxUvsI QDMQQnM4/5KR1sntVEM4Dtt5k5Px0dqep1+g7i8fgO+RrMAxON8OICLc6w2VmXk3bx7H amH5FB8m41pIIuvUbMx8Fci3oifPZ0fI0WfDN+e/4+c5AhkfnvVZlVoVUugEfcoHEqVV Ywmjb0DrQBUQ5txWG17eV7a0RI/BBUEEX70o/1ONkANeOuSwGyA5vnmO3UH6+BCcac/P z7Tw== X-Gm-Message-State: ALoCoQnv6WBzdrOHhlvQvdt6BB9Sw2sdowwnAXiUX5RhwnjM7nw4Tp/ahcr96K+wSEWbMAtqdhDA X-Received: by 10.152.2.74 with SMTP id 10mr2793122las.36.1380652262026; Tue, 01 Oct 2013 11:31:02 -0700 (PDT) Received: from black.localnet ([93.100.122.208]) by mx.google.com with ESMTPSA id e4sm4831790lba.15.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 01 Oct 2013 11:31:01 -0700 (PDT) From: Valentine Barshak To: linux-sh@vger.kernel.org Cc: Simon Horman , Magnus Damm , Laurent Pinchart , Guennadi Liakhovetski Subject: [PATCH 6/6] arm: shmobile: lager: Disable unused PCI/USB channels Date: Tue, 1 Oct 2013 22:30:51 +0400 Message-Id: <1380652251-8143-7-git-send-email-valentine.barshak@cogentembedded.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1380652251-8143-1-git-send-email-valentine.barshak@cogentembedded.com> References: <1380652251-8143-1-git-send-email-valentine.barshak@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows to configure USB channels in the USBHS UGCTRL2 register, based on the flags value, passed to the lager_add_usb_devices() function. A USB channel is configured as PCI USB host if the corresponding bit in "flags" is set. Otherwise, the channel is either configured as USBHS/USBSS (channel 0/1) or disabled (channel 1). If USBHS gadget driver is enabled, channel 0 is configured as USBHS on Lager. Otherwise it is set as PCI USB host. In addition, the following switches have to be set correctly for the USB channel 0 configuration: SW5: pin1; SW6: pin1 -> PCI USB Host SW5: neutral; SW6: pin2 -> USB Function (VBUS always connected) SW5: pin3: SW6: pin2 -> USB Function (VBUS is connected only if GP5_18 pin is high) Signed-off-by: Valentine Barshak --- arch/arm/mach-shmobile/board-lager.c | 114 ++++++++++++++++++++++++++++++++--- 1 file changed, 105 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 08236fb..6926b85 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -168,7 +168,6 @@ static const struct resource ether_resources[] __initconst = { }; /* USBHS */ -#if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) static const struct resource usbhs_resources[] __initconst = { DEFINE_RES_MEM(0xe6590000, 0x200), DEFINE_RES_IRQ(gic_spi(107)), @@ -191,6 +190,7 @@ static const struct resource usbhs_resources[] __initconst = { #define USBHS_UGSTS_REG 0x190 #define USBHS_UGSTS_LOCK (3 << 0) +#if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) struct usbhs_private { struct renesas_usbhs_platform_info info; struct platform_device *pdev; @@ -309,9 +309,17 @@ static struct usbhs_private usbhs_priv __initdata = { * device present on each one. This gives us 3 USB host channels. * Channel 0 is shared with the USBHS function module. * Channel 2 is shared with the USBSS (XHCI) device. + * USB channels configuration is set in the USBHS_UGCTRL2_REG + * register of the USBHS function block. + * In addition, the following switches have to be set correctly + * for the USB channel 0 configuration: + * SW5: pin1; SW6: pin1 -> PCI USB Host + * SW5: neutral; SW6: pin2 -> USB Function (VBUS always connected) + * SW5: pin3: SW6: pin2 -> USB Function (VBUS is connected only + * if GP5_18 pin is high) */ #if IS_ENABLED(CONFIG_PCI) -static const struct resource pci_resources[] __initconst = { +static struct resource pci_resources[] __initdata = { /* Internal PCI0 */ DEFINE_RES_MEM_NAMED(0xee080000, 0x10000, "PCI0 MEM"), DEFINE_RES_MEM_NAMED(0xee090000, 0x10000, "PCI0 CFG"), @@ -326,15 +334,104 @@ static const struct resource pci_resources[] __initconst = { DEFINE_RES_IRQ(gic_spi(113)), }; -#define lager_register_pci() \ - platform_device_register_simple("pci-rcar-gen2", \ - -1, pci_resources, \ - ARRAY_SIZE(pci_resources)) +/* + * Disable PCI controller if the corresponding bit in "flags" + * is not set and register PCI controllers + */ +static void __init lager_register_pci(u32 flags) +{ + int i; + + /* Disable unused PCI controllers */ + for (i = 0; i < ARRAY_SIZE(pci_resources); i += 3) { + if (!(flags & 0x1)) + pci_resources[i].flags |= IORESOURCE_DISABLED; + flags >>= 1; + } + + platform_device_register_simple("pci-rcar-gen2", + -1, pci_resources, + ARRAY_SIZE(pci_resources)); } #else /* CONFIG_PCI */ -#define lager_register_pci() +#define lager_register_pci(flags) #endif /* CONFIG_PCI */ +#define LAGER_USB_PCI_ON(ch) (1 << (ch)) +#define LAGER_USB_PCI_OFF(ch) (0 << (ch)) + +#if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) || IS_ENABLED(CONFIG_PCI) +/* + * Fix-up and add USB devices. The USB channel is configured + * as PCI USB Host if the corresponding bit in flags is high. + * Otherwise, the channel is either configured as USBHS/USBSS + * (channel 0/2), or disabled (channel 1). + */ +static void __init lager_add_usb_devices(u32 flags) +{ + struct clk *clk; + void __iomem *hsusb_base; + u32 val; + + clk = clk_get(NULL, "hsusb"); + if (IS_ERR(clk)) { + /* Assume default settings */ + flags &= ~LAGER_USB_PCI_ON(0); + goto usb_init; + } + + hsusb_base = ioremap_nocache(usbhs_resources[0].start, + resource_size(usbhs_resources)); + if (!hsusb_base) { + /* Assume default settings */ + flags &= ~LAGER_USB_PCI_ON(0); + clk_put(clk); + goto usb_init; + } + + /* Enable USBHS clocks */ + clk_enable(clk); + + /* Set USB channels in USBHS UGCTRL2 register */ + val = ioread32(hsusb_base + USBHS_UGCTRL2_REG) & + ~(USBHS_UGCTRL2_USB0_HS | USBHS_UGCTRL2_USB2_SS); + + val |= (flags & LAGER_USB_PCI_ON(0)) ? + USBHS_UGCTRL2_USB0_PCI : USBHS_UGCTRL2_USB0_HS; + val |= (flags & LAGER_USB_PCI_ON(2)) ? + USBHS_UGCTRL2_USB2_PCI : USBHS_UGCTRL2_USB2_SS; + iowrite32(val, hsusb_base + USBHS_UGCTRL2_REG); + iounmap(hsusb_base); + +usb_init: + if (!(flags & LAGER_USB_PCI_ON(0))) + lager_register_usbhs(); + + lager_register_pci(flags); +} +#else /* CONFIG_USB_RENESAS_USBHS_UDC || CONFIG_PCI */ +#define lager_add_usb_devices(flags) +#endif /* CONFIG_USB_RENESAS_USBHS_UDC || CONFIG_PCI */ + +#if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) +/* USB channel 0 is USBHS function */ +#define LAGER_USB0_FLAG LAGER_USB_PCI_OFF(0) +#define LAGER_USB0_DEVNAME "renesas_usbhs" +#else +/* USB channel 0 is PCI USB Host */ +#define LAGER_USB0_FLAG LAGER_USB_PCI_ON(0) +#define LAGER_USB0_DEVNAME "pci-rcar-gen2" +#endif + +/* USB channel 1 is PCI USB Host */ +#define LAGER_USB1_FLAG LAGER_USB_PCI_ON(1) +/* USB channel 2 is PCI USB Host */ +#define LAGER_USB2_FLAG LAGER_USB_PCI_ON(2) + +#define LAGER_USB_FLAGS (LAGER_USB0_FLAG | \ + LAGER_USB1_FLAG | \ + LAGER_USB2_FLAG) + static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", @@ -401,8 +498,7 @@ static void __init lager_add_standard_devices(void) ðer_pdata, sizeof(ether_pdata)); lager_add_du_device(); - lager_register_usbhs(); - lager_register_pci(); + lager_add_usb_devices(LAGER_USB_FLAGS); } /*