From patchwork Thu Oct 10 19:08:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentine Barshak X-Patchwork-Id: 3018301 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1C7F7BF924 for ; Thu, 10 Oct 2013 19:08:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CCB28202C7 for ; Thu, 10 Oct 2013 19:08:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 827DA202F0 for ; Thu, 10 Oct 2013 19:08:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757087Ab3JJTIJ (ORCPT ); Thu, 10 Oct 2013 15:08:09 -0400 Received: from mail-la0-f42.google.com ([209.85.215.42]:56086 "EHLO mail-la0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756783Ab3JJTIH (ORCPT ); Thu, 10 Oct 2013 15:08:07 -0400 Received: by mail-la0-f42.google.com with SMTP id ep20so2517155lab.29 for ; Thu, 10 Oct 2013 12:08:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=9Zq8YE1tCVwwcYYHxaBRbHhwtltY94TBm/35ISTpiI4=; b=Rffx6zXck3veDU3hDfIXmOxARrYfiOFNe1Rv/AKgYKC5vhF1x7ooHcKv6OFPcC6qM5 ULzJzSjmEBcZcVNhsPrVvEVye9xptm3PYcUPzzdKTwnmIDZqBd/fvPdK3mVNZv/0mV8S xvS0eUXPg7iIiaSAxRzH+O3hk0hFuyi8EvcxuyrA/dTwh2RIzacWuZlsFm3xJJlW7Loc 6sicPg3mGLiBM37106VKWjcJ+19EZKoBkKbybnCFwCmC1Gyj+i7PlIOkc/1+hYCAnvbo /kZ4yHI6ZZbXPJuCOV5u1W9ZQabkTN0Qv7Jr9umNEykg5mb2EM38Xq5Bg3NGhVwIoybm mOlA== X-Gm-Message-State: ALoCoQka9AMgV004Qhw0gQofcpzzxYoTAiZZlNjyJ0flmxn0iErUGdH8mJ1Bb/Pt91fZ3lHj5fEx X-Received: by 10.152.20.74 with SMTP id l10mr2315727lae.46.1381432085890; Thu, 10 Oct 2013 12:08:05 -0700 (PDT) Received: from black.localnet ([93.100.122.208]) by mx.google.com with ESMTPSA id o1sm41448678lah.8.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 10 Oct 2013 12:08:05 -0700 (PDT) From: Valentine Barshak To: linux-sh@vger.kernel.org, linux-ide@vger.kernel.org Cc: Simon Horman , Magnus Damm , Tejun Heo , Vladimir Barinov , Kuninori Morimoto , Laurent Pinchart , Guennadi Liakhovetski Subject: [PATCH] ata: sata_rcar: Add RCAR Gen2 SATA PHY support Date: Thu, 10 Oct 2013 23:08:03 +0400 Message-Id: <1381432083-3684-1-git-send-email-valentine.barshak@cogentembedded.com> X-Mailer: git-send-email 1.8.3.1 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP RCAR Gen2 SoC has a different phy which is not compatible with the older H1/M1 versions. This adds OF/platform device table and PHY initialization callbacks for H2/M2 (Gen2) SoC. PHY initialization method is chosen based on the device id. Default PHY settings are applied for Gen2 SoC, which should suit the available Gen2 boards. Signed-off-by: Valentine Barshak --- drivers/ata/sata_rcar.c | 108 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 94 insertions(+), 14 deletions(-) diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c index c2d95e9..45af29f 100644 --- a/drivers/ata/sata_rcar.c +++ b/drivers/ata/sata_rcar.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -118,17 +119,42 @@ #define SATAPCTLR3_REG 0x5A #define SATAPCTLR4_REG 0x60 +/* Gen2 Physical Layer Control Registers */ +#define RCAR_GEN2_PHY_CTL1_REG 0x1704 +#define RCAR_GEN2_PHY_CTL1 0x34180002 +#define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */ + +#define RCAR_GEN2_PHY_CTL2_REG 0x170C +#define RCAR_GEN2_PHY_CTL2 0x00002303 + +#define RCAR_GEN2_PHY_CTL3_REG 0x171C +#define RCAR_GEN2_PHY_CTL3 0x000B0194 + +#define RCAR_GEN2_PHY_CTL4_REG 0x1724 +#define RCAR_GEN2_PHY_CTL4 0x00030994 + +#define RCAR_GEN2_PHY_CTL5_REG 0x1740 +#define RCAR_GEN2_PHY_CTL5 0x03004001 +#define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ +#define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ + /* Descriptor table word 0 bit (when DTA32M = 1) */ #define SATA_RCAR_DTEND BIT(0) #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL +enum sata_rcar_type { + RCAR_SATA, + RCAR_GEN2_SATA, +}; + struct sata_rcar_priv { void __iomem *base; struct clk *clk; + enum sata_rcar_type type; }; -static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) +static void sata_rcar_phy_preinit(struct sata_rcar_priv *priv) { void __iomem *base = priv->base; @@ -170,6 +196,29 @@ static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, iowrite32(0, base + SATAPHYADDR_REG); } +static void sata_rcar_phy_init(struct sata_rcar_priv *priv) +{ + sata_rcar_phy_preinit(priv); + sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); + sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); + sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); + sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); + sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); + sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); +} + +static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv) +{ + void __iomem *base = priv->base; + + iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); + iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); + iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); + iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); + iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC | + RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); +} + static void sata_rcar_freeze(struct ata_port *ap) { struct sata_rcar_priv *priv = ap->host->private_data; @@ -738,13 +787,17 @@ static void sata_rcar_init_controller(struct ata_host *host) u32 val; /* reset and setup phy */ - sata_rcar_phy_initialize(priv); - sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); - sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); - sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); - sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); - sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); - sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); + switch (priv->type) { + case RCAR_GEN2_SATA: + sata_rcar_gen2_phy_init(priv); + break; + case RCAR_SATA: + sata_rcar_phy_init(priv); + break; + default: + dev_warn(host->dev, "SATA PHY is not initialized\n"); + break; + } /* SATA-IP reset state */ val = ioread32(base + ATAPI_CONTROL1_REG); @@ -770,8 +823,34 @@ static void sata_rcar_init_controller(struct ata_host *host) iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); } +static struct of_device_id sata_rcar_match[] = { + { + .compatible = "renesas,rcar-sata", + .data = (void *)RCAR_SATA + }, + { + .compatible = "renesas,sata-r8a7790", + .data = (void *)RCAR_GEN2_SATA + }, + { + .compatible = "renesas,sata-r8a7791", + .data = (void *)RCAR_GEN2_SATA + }, + {}, +}; +MODULE_DEVICE_TABLE(of, sata_rcar_match); + +static const struct platform_device_id sata_rcar_id_table[] = { + { "sata_rcar", RCAR_SATA }, + { "sata-r8a7790", RCAR_GEN2_SATA }, + { "sata-r8a7791", RCAR_GEN2_SATA }, + { }, +}; +MODULE_DEVICE_TABLE(platform, sata_rcat_id_table); + static int sata_rcar_probe(struct platform_device *pdev) { + const struct of_device_id *of_id; struct ata_host *host; struct sata_rcar_priv *priv; struct resource *mem; @@ -787,6 +866,12 @@ static int sata_rcar_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + of_id = of_match_device(sata_rcar_match, &pdev->dev); + if (of_id) + priv->type = (enum sata_rcar_type)of_id->data; + else + priv->type = platform_get_device_id(pdev)->driver_data; + priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "failed to get access to sata clock\n"); @@ -892,15 +977,10 @@ static const struct dev_pm_ops sata_rcar_pm_ops = { }; #endif -static struct of_device_id sata_rcar_match[] = { - { .compatible = "renesas,rcar-sata", }, - {}, -}; -MODULE_DEVICE_TABLE(of, sata_rcar_match); - static struct platform_driver sata_rcar_driver = { .probe = sata_rcar_probe, .remove = sata_rcar_remove, + .id_table = sata_rcar_id_table, .driver = { .name = DRV_NAME, .owner = THIS_MODULE,