From patchwork Fri Dec 13 11:52:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentine Barshak X-Patchwork-Id: 3339731 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5C8699F380 for ; Fri, 13 Dec 2013 11:52:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A3CDF20671 for ; Fri, 13 Dec 2013 11:52:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8A76C207C5 for ; Fri, 13 Dec 2013 11:52:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752546Ab3LMLws (ORCPT ); Fri, 13 Dec 2013 06:52:48 -0500 Received: from mail-la0-f53.google.com ([209.85.215.53]:34095 "EHLO mail-la0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752353Ab3LMLwr (ORCPT ); Fri, 13 Dec 2013 06:52:47 -0500 Received: by mail-la0-f53.google.com with SMTP id mc6so1293888lab.40 for ; Fri, 13 Dec 2013 03:52:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IlhFBWx4286WayiE+qvTQ4ZGaR6X55DwSDAlGlj8ZHU=; b=TG8PDhUs2QsrB5NZOt2CN/i0BekmjM75GzADxc88Jedr/15nQsQZBV4T7uBm4LJiMR xxH+wo0qYnJ1qqvpRyxRI6kpD7+FMk7yAaoC58DuHvzq9GijX9zutfI5e6AhqsN+MFlc sl8bqzXdwSqKUPptIcB3xikjZL2aa6shitPZUVZx7GN03K6ZwMGcZ7qTuBUVeLPA2vir nG5AR5JWyCqMbAUKXUZyhWvw3NaGwMQjHuE5wiZwXvtcr1V+QKwRQXS8tacIyo8wHvB7 52mXwuaCg9ihkHDjaH8OPRFyTyr5SzUCKjUOIUDQGsIMPjqFjhAtYrt6yJEbHkNfN1m+ TbMQ== X-Gm-Message-State: ALoCoQmdPutnfrIGynBtUTwJiNSnU54mqb23iaJn2HMbECS525RTuQ0vKLLVIk0R3yFIatxZdb0Z X-Received: by 10.152.87.211 with SMTP id ba19mr1286567lab.13.1386935566553; Fri, 13 Dec 2013 03:52:46 -0800 (PST) Received: from black.localnet ([93.100.122.208]) by mx.google.com with ESMTPSA id e10sm3721190laa.6.2013.12.13.03.52.44 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Dec 2013 03:52:45 -0800 (PST) From: Valentine Barshak To: linux-sh@vger.kernel.org Cc: Simon Horman , Magnus Damm , Kuninori Morimoto , Laurent Pinchart Subject: [PATCH 2/2] arm: shmobile: r8a7790: Add SATA clock support Date: Fri, 13 Dec 2013 15:52:40 +0400 Message-Id: <1386935560-16739-3-git-send-email-valentine.barshak@cogentembedded.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1386935560-16739-1-git-send-email-valentine.barshak@cogentembedded.com> References: <1386935560-16739-1-git-send-email-valentine.barshak@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_FRT_STOCK2, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds SATA 0/1 clock support. External 100MHz SATA 0/1 reference clock is supposed to be applied to the following pins: CICREFP0_SATA/CICREFP1_SATA; CICREFN0_SATA/CICREFN1_SATA. Signed-off-by: Valentine Barshak --- arch/arm/mach-shmobile/clock-r8a7790.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 3e27200..c4b567b 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -73,6 +73,18 @@ static struct clk extal_clk = { .mapping = &cpg_mapping, }; +/* External SATA0 reference clock: 100MHz fixed */ +static struct clk sata0_clk = { + .rate = 100000000, + .mapping = &cpg_mapping, +}; + +/* External SATA1 reference clock: 100MHz fixed */ +static struct clk sata1_clk = { + .rate = 100000000, + .mapping = &cpg_mapping, +}; + static struct sh_clk_ops followparent_clk_ops = { .recalc = followparent_recalc, }; @@ -140,6 +152,8 @@ static struct clk *main_clks[] = { &ddr_clk, &mp_clk, &cp_clk, + &sata0_clk, + &sata1_clk, }; /* SDHI (DIV4) clock */ @@ -187,6 +201,7 @@ enum { MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005, MSTP931, MSTP930, MSTP929, MSTP928, MSTP917, + MSTP815, MSTP814, MSTP813, MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, MSTP717, MSTP716, @@ -215,6 +230,8 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */ [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */ [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */ + [MSTP815] = SH_CLK_MSTP32(&sata0_clk, SMSTPCR8, 15, 0), /* SATA0 */ + [MSTP814] = SH_CLK_MSTP32(&sata1_clk, SMSTPCR8, 14, 0), /* SATA1 */ [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ @@ -321,6 +338,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]), CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]), CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]), + CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]), + CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]), /* ICK */ CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),