From patchwork Wed Dec 18 12:44:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentine Barshak X-Patchwork-Id: 3369991 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 428AA9F314 for ; Wed, 18 Dec 2013 12:44:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05C7A20457 for ; Wed, 18 Dec 2013 12:44:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B8D502044B for ; Wed, 18 Dec 2013 12:44:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752836Ab3LRMob (ORCPT ); Wed, 18 Dec 2013 07:44:31 -0500 Received: from mail-la0-f49.google.com ([209.85.215.49]:38680 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753313Ab3LRMoa (ORCPT ); Wed, 18 Dec 2013 07:44:30 -0500 Received: by mail-la0-f49.google.com with SMTP id er20so3757756lab.8 for ; Wed, 18 Dec 2013 04:44:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cY52c5EG+UQH9tfqjdDnemYun4Ap1TDBXoZrEJWRNBU=; b=ZiISnaoRlyR6Mxm2TIqyDLw+BBlKQhvJYAg5M2ew9gwgKunrB2pYp3+uxNEVzJsFvH Dluh1jwHwOb1OFlzYA/z/nh7aSdZmIz/aNYbGVGVxujx2jEzgu0nPbJfvPxbVbUGHzVa Vj1lpAkZ2izQ97jJWERUYHc9PQmnRhvuT4uPUJ8MZEMqUAMRB/ehQR6rK+YpAeE8RUcw BXaeSPs7DWIS3do4oDdIuKs5O9EpS0DrWXAm8lx/kafbT/8HbVh+I1vST0u8AiAYZRYk jby5VIbhAXHWgAZz3KKlrU1oZmesfZEFK1Q44revHC9+sk8oIodedseFcHz0WNOMqg9p /rKw== X-Gm-Message-State: ALoCoQl7/QspzfSq18NFsz3yOO5qyAR89+DEuXOMrjFBic543iz47VFiGtA3Lguvfg3NisVf2WBe X-Received: by 10.112.151.74 with SMTP id uo10mr1482712lbb.45.1387370669105; Wed, 18 Dec 2013 04:44:29 -0800 (PST) Received: from black.localnet ([93.100.122.208]) by mx.google.com with ESMTPSA id y11sm3961615lbm.13.2013.12.18.04.44.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Dec 2013 04:44:28 -0800 (PST) From: Valentine Barshak To: linux-sh@vger.kernel.org Cc: Simon Horman , Magnus Damm , Kuninori Morimoto , Laurent Pinchart Subject: [PATCH 4/5] arm: shmobile: lager: Add internal PCI support Date: Wed, 18 Dec 2013 16:44:19 +0400 Message-Id: <1387370660-20481-5-git-send-email-valentine.barshak@cogentembedded.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1387370660-20481-1-git-send-email-valentine.barshak@cogentembedded.com> References: <1387370660-20481-1-git-send-email-valentine.barshak@cogentembedded.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds internal PCI USB host devices to R-Car H2 Lager board. If USBHS device is disabled, channel 0 is configured as PCI USB host. Otherwise, it is configured as USBHS. The USB phy is bound bound to either USB host or USBHS device respectively. We don't bind USB phy to the PCI host at channel 2 since it's configured as PCI host by default and is not currently used by anything else. Signed-off-by: Valentine Barshak --- arch/arm/mach-shmobile/board-lager.c | 90 +++++++++++++++++++++++++++++++----- 1 file changed, 79 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index f1efe8f..af00f1d 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -375,7 +375,11 @@ static struct usbhs_private usbhs_priv __initdata = { } }; -static void __init lager_register_usbhs(void) +/* Channel 0 is USBHS */ +#define LAGER_USB0_PCI 0 +#define LAGER_USB0_NAME "renesas_usbhs" + +static void __init lager_add_usb0_device(void) { usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2"); platform_device_register_resndata(&platform_bus, @@ -386,19 +390,82 @@ static void __init lager_register_usbhs(void) sizeof(usbhs_priv.info)); } #else /* CONFIG_USB_RENESAS_USBHS_UDC */ -static inline void lager_register_usbhs(void) { } + +/* Channel 0 is PCI USB host */ +#define LAGER_USB0_PCI 1 +#define LAGER_USB0_NAME "pci-rcar-gen2.0" + +/* Internal PCI0 */ +static const struct resource pci0_resources[] __initconst = { + DEFINE_RES_MEM(0xee090000, 0x10000), /* CFG */ + DEFINE_RES_MEM(0xee080000, 0x10000), /* MEM */ + DEFINE_RES_IRQ(gic_spi(108)), +}; + +static void __init lager_add_usb0_device(void) +{ + usb_bind_phy("0000:00:01.0", 0, "usb_phy_rcar_gen2"); + usb_bind_phy("0000:00:02.0", 0, "usb_phy_rcar_gen2"); + platform_device_register_simple("pci-rcar-gen2", + 0, pci0_resources, + ARRAY_SIZE(pci0_resources)); +} #endif /* CONFIG_USB_RENESAS_USBHS_UDC */ +/* Internal PCI1 */ +static const struct resource pci1_resources[] __initconst = { + DEFINE_RES_MEM(0xee0b0000, 0x10000), /* CFG */ + DEFINE_RES_MEM(0xee0a0000, 0x10000), /* MEM */ + DEFINE_RES_IRQ(gic_spi(112)), +}; + +static void __init lager_add_usb1_device(void) +{ + platform_device_register_simple("pci-rcar-gen2", + 1, pci1_resources, + ARRAY_SIZE(pci1_resources)); +} + +/* Channel 2 is PCI USB host */ +#define LAGER_USB2_PCI 1 + +/* Internal PCI2 */ +static const struct resource pci2_resources[] __initconst = { + DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */ + DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */ + DEFINE_RES_IRQ(gic_spi(113)), +}; + +static void __init lager_add_usb2_device(void) +{ + platform_device_register_simple("pci-rcar-gen2", + 2, pci2_resources, + ARRAY_SIZE(pci2_resources)); +} + /* USBHS PHY */ static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = { - .chan0_pci = 0, /* Channel 0 is USBHS */ - .chan2_pci = 1, /* Channel 2 is PCI USB */ + .chan0_pci = LAGER_USB0_PCI, + .chan2_pci = LAGER_USB2_PCI, }; static const struct resource usbhs_phy_resources[] __initconst = { DEFINE_RES_MEM(0xe6590100, 0x100), }; +/* Add all available USB devices */ +static void __init lager_add_usb_devices(void) +{ + platform_device_register_resndata(&platform_bus, "usb_phy_rcar_gen2", + -1, usbhs_phy_resources, + ARRAY_SIZE(usbhs_phy_resources), + &usbhs_phy_pdata, + sizeof(usbhs_phy_pdata)); + lager_add_usb0_device(); + lager_add_usb1_device(); + lager_add_usb2_device(); +} + static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", @@ -428,8 +495,14 @@ static const struct pinctrl_map lager_pinctrl_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", "intc_irq0", "intc"), /* USB0 */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + PIN_MAP_MUX_GROUP_DEFAULT(LAGER_USB0_NAME, "pfc-r8a7790", "usb0", "usb0"), + /* USB1 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + "usb1", "usb1"), + /* USB2 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", + "usb2", "usb2"), }; static void __init lager_add_standard_devices(void) @@ -480,12 +553,7 @@ static void __init lager_add_standard_devices(void) platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++, &vccq_sdhi2_info, sizeof(struct gpio_regulator_config)); - platform_device_register_resndata(&platform_bus, "usb_phy_rcar_gen2", - -1, usbhs_phy_resources, - ARRAY_SIZE(usbhs_phy_resources), - &usbhs_phy_pdata, - sizeof(usbhs_phy_pdata)); - lager_register_usbhs(); + lager_add_usb_devices(); } /*